Shadow Ram Copy - Making an 8 Bit pipelined CPU - Part 96

[@Artentus]

I'm glad I found this channel. Over the last couple days I've been binge-watching the entire series.

[@weirdboyjim]

Good to hear you have found it interesting!

[@akkudakkupl]

Same here mate, it's probably the most advanced DIY CPU on KZbin and the videos are educational 🙂

[@matthewpeterson5159]

This series has become one of my absolute favorites of all time, if not my favorite, in its 'genre', if you will. Your work is truly inspirational! Kind of encourages to continue trying to do more and more ambitious things with (hobby) electronics. Thank you! :)

[@weirdboyjim]

Glad you enjoy it Scitoshi!

[@victormuckleston]

you may be alone during your success, but we are all here to appreciate it through the video. excelent work !

[@weirdboyjim]

Glad you are finding it interesting thanks Victor!

[@Revolution1200]

Another fantastic and educational video, the cpu looks amazing, have been following along since the start and look forward to these when I get the youtube notification, keep up the great work

[@weirdboyjim]

Much appreciated! Glad you are finding it interesting.

[@AjinkyaMahajan]

Great work, James. It had come a long way since the breadboard Prototyping Cheers

[@weirdboyjim]

Thanks Ajinkya!

[@damouze]

And yet another step. I am impressed! I would have never thought of building a circuit like this in hardware. Instead, I would probably have ended up with a small piece of code that would have copied itself to a higher (RAM) address in memory and have jumped to that address afterwards. But then again, I am mostly a software guy and not really experienced in electrical design. Very ingenious. Keep it up!

[@weirdboyjim]

Thanks Damouze. I did think about a copy (coupled with a banking system to swap ram in over the rom) but with this system it's easier to use the single step for debugging, don't want to have to step the copy.

[@LeoBerardino]

On each new episode I'm becoming more amazed by this project.

[@weirdboyjim]

Glad your still finding it interesting Leonardo and thanks for the continued support!

[@erikrodriguez7112]

Greetings! Love what you are doing with Ben’s starter. I am working on a similar project. I am basing my work on yours and Ben’s efforts. Having taken electronics classes in high school and now in my 50’s I don’t remember a lot of it. It would be extremely helpful if you could include R and C values in your circuits. Example: your circuit for the shadow ram excludes most of the R and C value. Some of which are critical especially around the 555 and the power supervisor. Thanks for all your work! I will be donating to your channel soon after Christmas.

[@weirdboyjim]

Thanks! Apologies if I miss out some of the values, around those 555's it's often because I'm leaving my options open as there are multiple combinations of values that give the same result.

[@erikrodriguez7112]

Could you tell me the values around the power monitor?

[@WesBrownStories]

It looks freaking awesome!

[@weirdboyjim]

Thanks Wes!

[@matthewpeterson5159]

I find it very interesting that you chose to implement this in the way you did; it's the (at least) second implementation of this style that I've seen/heard of. In my latest 6502 computer I have used a scheme where I allow the computer to select whether ROM or upper RAM is enabled, just with an extra bit thrown into the mix of the decode logic. Just out of curiosity, did you consider this scheme? If so, how did you choose to implement the copy-on-reset hardware instead? Thanks! :)

[@weirdboyjim]

If you watch video 91 (kzbin.info/www/bejne/aWrKn3d3nKh9mbc ) I do talk about a number of different options. What you describe is basic banking which I mention. I picked this for a couple of reason, one is the simplicity of the programming model but there is another reason that will become clear in the future.

[@matthewpeterson5159]

@@weirdboyjim Awesome, thanks!

[@matthewpeterson5159]

Just noticed, my memory is frighteningly bad sometimes -- I'd already seen episode 91 and commented and gotten a response from you! My bad lol

[@m1geo]

Won't be long now until you have the Arduino bootloader on there! 😉😉 Great work as always!

[@weirdboyjim]

Something along those lines yes, but I don't think the Arduino ide is quite ready for an 8-bit micro. I have thought about it if I ever do a 32 bit build though.

[@m1geo]

@@weirdboyjim oh my. Id donate/help with a 32bit version!

[@UsagiElectric]

Another excellent video! Could this potentially pave the way for loading programs through an external media, like a floppy or tape, into RAM for running? I'm imaging the Snek game on a Floppy that gets read into RAM at reset and then executes.

[@weirdboyjim]

Thanks! I'd definitely like some storage of code that would allow me to select programs without changing chips. There are a couple of different options on the table still but I'm veering towards a storage system that I can also access from the pc.

[@m1geo]

@@weirdboyjim bootloader in ROM that'll read binaries in over the UART?

[@weirdboyjim]

@@m1geo That's the idea.

[@sebbothebushnerd]

@13:11 Did you drop the LED display in a tin of paint? :O Hahaha. Another great video as always!

[@weirdboyjim]

I think those are actually paint scratched off. I only have a few of the 8 led bar graphs and I haven't treated them as well as I might.

[@Quxxy]

Nice. I can imagine the new memory board being quite a bit busier given all the extra components. I briefly imagined a multi-tiered module, which got me imagining each module slowly stacking up multiple PCB layers like skyscrapers to keep in a reasonable footprint... then I remembered the PCB has a back side.

[@weirdboyjim]

I will try and avoid the back if I can. The memory board at the moment is quite sparse.

[@Quxxy]

@@weirdboyjim It *does* look better with all the components exposed. I don't hang stuff on the walls (never saw the point), but I've begun thinking that something akin to your CPU (or if I could afford it, a MOnSter 6502) would be cool.

[@AmauryJacquot]

this could be also added to the microcode roms circuits

[@weirdboyjim]

Not without a lot of extra circuitry over there, and I wanted to keep the changes confined to the memory board as much as possible.

[@AmauryJacquot]

@@weirdboyjim sure, I meant, add the same kind of functionnality to each board at a later date

[@weirdboyjim]

Ahh yes, I think I read your comment wrong. You are thinking about switching the Control roms to ram for the speed. That did occur to me, especially when I was thinking about a stand alone rom emulator board. But I've been planning to burn my control roms to a set of "AT27C256R-45PU" when it's settled which gives me a nice speed boost.

[@akkudakkupl]

@@weirdboyjim 10MHz clock incoming? 🙂

[@harshchikorde9495]

I have just started your series of building a cpu (watched uptill number 36) can u plz tell in which video have you revealed the assembly code that you were writing instructions in to load instructions in EEPROM and also what software is it that allows u to create assembly instructions?

[@weirdboyjim]

I have 2 main programs that I think you are asking about. Firstly I have written an assembler for the processor, that allows me to turn an assembly language program into machine code to put on a program rom. The second program is for building the rom data for the rom chips in the pipeline. I first show both of those programs in video 19 although they have been developed quite a bit since then.

[@TheEmbeddedHobbyist]

I find it quite interesting that you have not killed any chips while hot plugging them in the breadboard. Keep um comming James.

[@weirdboyjim]

Lets not talk about the ones I soldered back to front ;-)

[@jimmy21584]

This one was super interesting - like coding in hardware.

[@weirdboyjim]

Indeed. Actually one option I considered was to wire the rom into an IO arrangement and then code a copy routine up in a diode matrix.

[@theowinters6314]

Well, you're about 1/3rd of the way to a DMA circuit, though not sure how useful that would be with your processor. As an aside, one thing I've done is set up a couple of banks of LEDs and resistor nets on a small breadboard, that way I can just plug in a couple of wires anytime I need them. It only saves a few seconds really, but it's nice to have that ready and waiting in once package.

[@weirdboyjim]

I keep meaning to create a couple of small pcb module boards with LED arrays on for things like that.

[@neilsharman7876]

Squeezing all these new chips onto a new PCB could be a lot of fun. Have you considered using a pair 74HCT393's as the counters instead of four 74HCT193's?

[@weirdboyjim]

I guess that's possible. But I do have a bunch of 193's in both dip and smd. The 393's would save me 2 chips but I'd have to order the parts in and then wait.

[@dennisdecoene]

That is the coolest thing ever. Remember my comment on the previous video? Don't know how but I seem to have missed ep91, hence my rather daft comment. But still, Is it the plan to not have to wrestle anymore with eeproms in the future?

[@weirdboyjim]

Would indeed be nice if I could get code to the cpu quicker.

[@bradywb98]

I’d like to do a ROM to RAM copy module for the instruction decoder and microcode EEPROMs

[@weirdboyjim]

I can understand why, The sram is much faster. But replicating this circuit out how many time you need could be a pain. Might be worth trying to find a way to share more circuitry.

[@bradywb98]

@@weirdboyjim If the instruction decoder and microcode EEPROMs have the same size then I think the circuit would only need to be built once, the counter address going to the corresponding ROMs for each RAM chip, but having separate data buses.

[@bradywb98]

@@weirdboyjim But yes, I'm thinking it'd be nice to also include shadow RAM has you've done here so perhaps there could be some trickery to share the copy circuit between both the control ROMs and the memory ROMs.

[@TheDefpom]

Have you thought about using a ZIF socket for the ROM IC?

[@weirdboyjim]

The memory board has always had a zif socket for the rom, the yellow pcb module you see plugs into it. That's just a temporary circuit to prototype the new functionality, when complete I'll get a "Memory v2" pcb made that will have the ram all as smd and a zif socket again for the rom. This should open up more options for getting code into the build though so I'll be burning less roms (I hope).

[@jerril42]

Thanks James, I like this versatile runtime model. Are you looking at some kind of mass storage? I can't remember if that was in the works. Great job coordinating the schematics with the prototype build; that must have been tricky.Take care. P.S. This would make an excellent Forth system.

[@weirdboyjim]

I want a system for uploading code via the UART, but I have some ideas on mass storage as well.

[@bradywb98]

I’d love to hear your thoughts on mass storage

[@alessiocaffi5992]

ok James, now let's write some verilog code for FPGA synthesis and build, ( it also would be a complex work for sure). great work. chreers

[@weirdboyjim]

Unlikely to convert this build to FPGA. If I were doing that I'd probably look at doing a 32 bit version and then there are some other changes I would make if there is no need to have separately sized address and general purpose registers.

[@alessiocaffi5992]

​@@weirdboyjimyes it was addressed to all of your fans, give it some time, maybe somebody will, if given details. Sure one could go much higher than 8 on the larger once (CISC RISC RIS-V)...

[@neilsharman7876]

Would it have been possible to use one of the existing address registers and just manipulate the control line of that to do most of the work?

[@weirdboyjim]

That's an interesting idea, but it would have been tricky to isolate all the control lines such that two different things can manage it. The other thing to think about is that for most processors the memory is external, so I didn't want to add any assumptions inside the real cpu components about memory.

[@jandevisser2385]

Please tell me you're James' brother. That would explain how you can keep up with the intricacies of his designs haha

[@neilsharman7876]

@@jandevisser2385 No sorry, James and I are not related.

[@drlazy1]

I dunno seems like a lot of chips for a one time memory copy. Is this circuit going to be used for something else? If you need speed you can get NOR flash down to 45ns if you don't mind a PLCC package, like this: SST39SF010A-45-4I-NHE, 70ns for DIP. With that you could do the copy in software. For hardware you just need to be able to select which chip sees the OE signal, writes always go to the RAM. If you don't have enough IO to do the switch you could use a 555.

[@weirdboyjim]

It's a mixture of things, the speed is nice. Having all of memory as Ram will be useful for a few things. I could have written copy code and put a selection system in but then if I was debugging I'd have to worry about stepping past the copy. I favored keeping everything for this in the memory module but I'm not presenting it as the right choice for everyone.

[@djc1402]

Now you have just RAM for the CPU is there any advantage to using self modifying code or do you think that is redundant / dangerous in a pipe-lined architecture? Personally I hate self modifying code and never use it. I am eagerly waiting for your VGA solution as I have had one on my 8-bit CPU build for over a year and it makes it feel like a 'real' computer.

[@weirdboyjim]

Self modifying code is sometimes really awesome for performance, used to do that a lot on early games but modern OS stop you doing it.

[@prtlwnft4028]

Hi James, you delayed the MemBridgeLoad signal by 1-4 or gates electable by jumper, but this signal is High from poweron and does not change during rom-copy, so it does not delay the WE signal? in my build WE is not delayed and therefor is active before data valid, what do i misunderstand?

[@weirdboyjim]

The signal from load is delayed as it goes low for the first half of the cycle and I needed to push it back relative to where all the inputs were ready on address and memdata. During the copy it's pulsed by the inverse clock however which is half a cycle behind the address changing.

[@prtlwnft4028]

@@weirdboyjim many thanks for quick answering! I think I have to check my schematic, is your schematic on EDA the actual one?

[@weirdboyjim]

@@prtlwnft4028 Yes, did you clone the circuit or make your own circuit based on my poorly vocalization?

[@detlevmustinger6328]

@@weirdboyjim both, finally I cloned your schematic

[@detlevmustinger6328]

on my proteus simulation it works fine, but in real life on pcb WE is too early

[@rickdearman9992]

Silly question, but why not load your program into the ram chip directly? Why use Ron as intermediate? I know you can't use an eerom programmer, but with an Arduino and a breadboard you can upload your binary file directly to it.

[@weirdboyjim]

That would leave my homebrew pipelined cpu dependent on an Arduino being actively involved in getting it to do anything. The ram upgrade has multiple purposes and reasons, but one is I'm hoping to write a boot loader that will let me have multiple ways of getting code into the system. Be nice to upload a new program for test over the UART.

[@reinoud6377]

Why didn't you use a flip flop that normally chipenables the rom but on first write switches permanently to ram? Would mean a copy routine though...

[@weirdboyjim]

That solution could suit some people. Two reasons why I didn't go with that, firstly the copy routine would be a pain to get past if I was trying to debug the code with stepping. Secondly it seems you can always get ram that's faster the eeprom, I'd rather not support the complexity of different speeds.

[@wafikiri_]

I've just ended the logical design of a processor, the virtual-to-physical address converter being last: configurable (two switches) EPROM size of 1, 2, 4 or 8K addresses × 16 bits for the kernel user, upper 1K EPROM addresses accessible by the non-kernel users (interrupt vectors and handler routines must reside there); configurable (two switches) I/O addressing space of 0.25, 1.25, 3.25 or 7.25K addresses; main SRAM virtually between I/O and EPROM, basic SRAM virtual addressing space below that of I/O, with first 48 addresses paged in 32 banks (for different sets of special and general-purpose registers), all 64K users getting 64K physical RAM addresses each. My design will serve to test a handful of inventions of mine. Having it multi-tasking was not a requisite but it's a way to test the inventions under more varied circumstances.

[@weirdboyjim]

I love hearing about other peoples builds but I think you might need to explain what you've been doing a bit more.

[@JohnDlugosz]

To bad you couldn't easily use one of the 16-bit counter/address registers that's already present. Then something like your original instruction fetch mock-up before building the pipeline would not just read each ROM location in order but write back to the same address as well.

[@weirdboyjim]

I did work out a couple of ways to short cut it like that, but one of the reasons I did it this way was to keep memory separate from the rest of the cpu.

[@twobob]

feels like that could run. gasp... a game ;)

[@weirdboyjim]

Now there is an idea...

[@edgeeffect]

Ahh... I see... I was thinking "this is fascinating... but why?!?!".... VGA explains it all... you need a shed-load of RAM for that there frame buffer.

[@weirdboyjim]

You might think that, but I couldn't possibly comment ;-)

[@akkudakkupl]

The CPU would have to give up every other clock to the video system, or video would need to access memory on opposite clock edges than the CPU. But then again VGA needs quite high bandwidth even at 640x480x16

[@naveenchavali8488]

@@weirdboyjim Hey James, I built a 800x600 character VGA video card (but has 320x240 actual resolution)(40x30 chars), if you are planning to do or are interested in anything similar I could create and upload the schematics, for you to have a look. Again this was an awesome video and great build, also an extremely cool continuation to Ben's computer, All the best to complete it :)

[@AJB2K3]

Ouu nice.

[@weirdboyjim]

Thanks Adam!

[@petesapwell]

🤓❤️😊

[@weirdboyjim]

🙂

[@detlevmustinger6328]

Hi James, thanks for that great project, since yesterday my rebuild of your CPU not only works in proteus simulation, but also on real PCB! Thanks for your videos/explanations, schematics, assembler, ctrlbuild-code and, and, and .. here you can see the primes at 725Hz kzbin.info/www/bejne/Z6PQnp-fodabmtk and here at 31kHz kzbin.info/www/bejne/eGOtg3aubcyIb6c

[@weirdboyjim]

Nicely done! It's really weird for me to see "my cpu, but not my cpu".