What is drain induced barrier lowering.

Welcome back to Semi Tech channel.
This video talks about the short short channel effect namely drain induced barrier lowering and leakage power dissipation due to it.

[@sakshisingh4197]

After lot of search here is a nice explanation

[@arushsharma9416]

much better than other lenghty monotonous videos thank you

[@arelyvazquez959]

Very nice explanation! thanks

[@sangphung6862]

your explanation is clear and easy to understand, thank you

[@dhruven19]

Very well explained sir !!

[@anithag4054]

Nice explanation.

[@GautamKumar-eo7jj]

VERY NICE EXPLANATION

[@jefferyaustin1571]

Hi Edu, If you want to have more audiences for your channel, please create more videos about MOSFET just like this video. Since the background is EE, it is easy to step in semiconductor field such as FINFET. That is one of the ways for you can have more audiences. Wish you the best.

[@semitech01]

Sure, we resumed it now. We'll put videos on Finfet soon

[@sadi9945]

source side depletion region cant increase because source is grounded as well as body is grounded too. so here barrier lowering is between source and channel.

[@bharatsuthar963830]

Very well explain sir...

[@vinayjjachar3365]

Nice explanation sir. Simple way of explanation for complex things is always good. Keep posting more videos like this

[@semitech01]

Thank you, I will . Keep watching!

[@supriyakaku1725]

Good explanation

[@jarikosonen4079]

I don't know why they draw higher voltage at lower curve... If this could be calculated somehow it could make it clear. Maybe one of the good explanations found.

[@rockingstone7700]

nice one bro

[@neerajhebbar7313]

Great 👍👏👏🥰

[@komalpatidar5207]

YOU HAVE EXPLAINED VERY WELL, EAGER TO SEE MORE VIDEOS. PLEASE MAKE MORE VIDEOS ON ANALOG CIRCUITS AND LAYOUTS

[@semitech01]

Sure. I will upload for sure

[@aswathipt8006]

Well explained

[@ramsaivelidandi6777]

good explanaton

[@prachitisharma]

Thanks a lot

[@semitech01]

Most welcome!

[@rockingstone7700]

bro please make a video on GIDL ....

[@semitech01]

Sure , I will put it out soon

[@AviSanX]

Hey what is that electron profile? Can someone explain it?

[@semitech01]

www.semanticscholar.org/paper/Gate-Induced-Drain-Leakage-Current-in-45-nm-CMOS-Yuan-Park/d8ae3db50fdf372b2442a625608be03012c34923 Please refer to the graph to understand current and electron profiles in detail. For energy band diagram and electron profile you can refer to figure 3 of below link www.researchgate.net/figure/Band-diagrams-of-a-gate-substrate-junction-and-b-gate-drain-edge-for-an-nFET_fig3_3140206

[@ranjithkumar-vh7ev]

When both the depletion regions met the device will off.am I correct ? Please correct me if i was wrong

[@niranjankumar3207]

Yes true that

[@rajneeshmishra551]

What is drain voltage

[@semitech01]

Hi Rajneesh, Drain voltage is always more than source voltage but has been represented by a low level curve . Typically drain voltage for short channels are 1.5 -1.8 V

[@prits721]

Great, thanks

[@psymmm]

great.

[@RESPECT-cd1md]

is drain induced barrier lowerig and punch throw effect are same

[@md.ramjanali6546]

Helpful explanation 🙏