Building a 6502 computer: Episode 5, The Reset Sequence (8 bit, apple, acorn, atari, commodore)

[@petertayler1712]

Great series of videos. I love the animations. Very helpful, and you don't see that much in these types of presentations.

[@XTronical]

Thank you for your support.

[@scubaflooba]

Great stuff, I am trying to fix my 1983 Oric1 and might test the 6502 this way, thank you so much

[@JarppaGuru]

18:42 raising edge clock? or active low like every other input lol

[@petermuller608]

Great explanation!

[@YNGBLD80]

hello mate interesting video- I'm trying to get my head around how the internal hardware finds it way to FFFC and FFDD after 7 clock cycles. Have you an literature you could recommend or possibly an explanation of the logic process within the 6502 that can explain how it manages to find the vector address/s upon reset. Cheers Franky

[@XTronical]

Obviously on a simple level that address is hardwired somewhere off from PC, and they'll be some sort of flip flop that enables this to flood into the PC. That's my guess anyway. I've seen internal schematics for the 6502 a while back, can't remember where, you will get a definite answer there but hard to interpret. I'm sorry I can't be more helpful. Perhaps have a look at one of the fpga implementations, they might do something very similar.

[@YNGBLD80]

@@XTronical Hello mate no issue thanks for the attempt to explain I've read a little further since this question and sort of got an understanding. Upon reset the 6502 puts a 0 through the IR as a result the Pal internal "rom" takes over an a sequence of 3 fake pushes on to the stack occur and a JMP instruction after 8 cycles its good to read the vector address. Not 100% across the internal sequence but hope that might make some sense to you

[@MikeK8LH]

Clocking the 6502 during reset works for me on a Rockwell R65C02 (producing a 7 cycle reset sequence). What is the state of CLOCK before you call Reset6502() in your original code? I initialize the clock pin to '1' (high) and my clock pulses go from high to low and back to high.

[@XTronical]

Thanks very much for the input. Yes the clock is high before entering reset and then low high low high to give two full cycles before bringing reset high again. I'm going to scope it out with a faster clock when I get time, see if the behaviour remains.

[@MikeK8LH]

@@XTronical I didn't see a digitalWrite(CLOCK,HIGH) instruction before calling Reset6502() and I believe pinMode(CLOCK,OUTPUT) by itself will leave the pin at '0' on an Uno or Nano (if you haven't previously set the output port latch bit) which implies that you may have only issued 1.5 clocks while reset was low. Perhaps that might explain the extra clock cycle (half clock cycle?) in the reset sequence?

[@XTronical]

Thanks again. Yes towards then end of the video I mention this. You can set it to input with pull up high and then an output and it will then start high. However looking at the video I actually set it to output first then then back to input! Surely I corrected this in my test... Well. I can't remember so you may be on to something here. Will test and get back to you. Really appreciate the help.

[@lishaton]

Not sure about this... So are you using an Arduino as nothing more than a reset line for the 6502? Isn't that a bit of overkill? I mean, surely, the more usual approach would be to use a schmitt inverter gate or two. Much cheaper. Please advise as I'm always ready to learn!

[@XTronical]

It does more than the reset line. It controls the clock also. I've also built a debugger system using the Arduino mega which monitors address and data lines. This is why this is being used here. It will not just be reset and is controlling the clock here as well.

[@garalddonohoe1094]

p̷r̷o̷m̷o̷s̷m̷ 🙌

[@TheKetsa]

Quite a slow moving project

[@XTronical]

Yes, sorry.