@@stevege8368 你发的链接中有两句话是这么说的,看好 “Imagine that a CPU has to load data from the L1 cache 100 times in a row. The L1 cache has a 1ns access latency and a 100 percent hit rate. It, therefore, takes our CPU 100 nanoseconds to perform this operation.” 和 “Now, assume the cache has a 99 percent hit rate, but the data the CPU actually needs for its 100th access is sitting in L2, with a 10-cycle (10ns) access latency. That means it takes the CPU 99 nanoseconds to perform the first 99 reads and 10 nanoseconds to perform the 100th. A 1 percent reduction in hit rate has just slowed the CPU down by 10 percent.” 这两句话总结起来就是,如果你的L1缓存的数据命中率不足够高的话,那不命中的数据就可能要轮到L2缓存去命中,而L1缓存的1%的非命中率则会导致读取100个数据的总延迟增加10%。以此类推,如果1个数据在没有被L1和L2命中的情况下而被L3命中了,那读取这100个数据的总延迟就比L1或L2命中都要高了。换句话讲,若想要读取数据的总延迟更低,就需要CPU的n级缓存(n越小越好)命中率越高越好。对比11700K和5800X两个u,你觉得哪个复合这一点呢?