In case of PCIe RC driver under uboot, why we need to define IO space in dts if using only MEM space we can see the endpoint? What is the purpose if IO space? And next question, with saying "Configuration Header space", we know that DBI address will point to PCIe controller where we can find configuration of PCIe, does that "Configuration Header Space" related to DBI or it related to CFG base address? Thanks a lot.

so far, this is best exapliantion. please upload vedio on LTSSM

Hi Sir, Can we get the notes for the lecture

Could you please explain LTSSM as well ?

Can you please provide subtitles? (CC)

Thanks for the explanation, will appreciate if you could share the Link to the Notes used in the Video.

Pls upload more.

17:32 64 bytes*

Short and helpful.

Hello Sir Could you please tell me Architecture diagram of PCIe to Memory (P2M) for Read...?

Very helpful lectures sir. ❤

PCIe nicely explained for beginners... Thanks so much.

hi, please correct me if I am wrong. During initialization, all connected Devices are assigned some address spaces from System Memory. And devices keep this info of memory space at their specific PCIe Configuration Space. Whenever a PCIe configuration cycle is generated, they monitor their dedicated adress block. Is it how it works? If it is so, how is that pCIe configuration cycle generated? thanks

hi, at 29.49, you say that data length (10 bits) can be up to 4096 Byte. But you can identify only up to 1024 byte with 10 bits. Am i wrong? thanks in advance.

Thank so much !

@PCIe sir, can we get the notes as well? btw, I am indebted to your for this valuable content delivery that too on free platform like youtube. thanks a lot. :)

Hi, Please share all the lectures Notes

Thank you, very helpful

how 1k word becomes 4kbtes @ 6:20

Whether CPU always go through Address port OxCF8 and Data port OxCFC for CAM; or this address will vary w.r.t PCIe gen? OxCF8 means Bus0 Device3 one function and register number is 0x37, OxCFC for data port can b read or write operation @pci3823

Grt explanation sir, thank you so much, if you can attach the slides or pdf which you were explaining would be helpful for us

At time 22:30 it is 2p24 - 2p4 = 2p20=1MB not 16 mb as ur saying.

I have doubt like after primary secondary and subordinate when bus device and function come into picture and when we will represent function with 1 and when will device numbers change in one branch device number is completely zero in other branch device number changes

Very good explanation in detail. Covered all sides of pcie

Please help with that

Need some testcases on this

Thanks Sir

Thanks

Great sir

Very good explanation, very helpful thank you

good explanation👍

Quality explaination 👍

Quality presination, as Naveen commented below, i have paid for PCIe training online and this is better.👍

Root complex

x12 not supported by pcie

Can I please have your notes as a document for all 4 videos? I will help a lot.🙂

great work, much appreciated. You should definitely post more LECTURES

at 13:26 you are saying that if (ENDPOINT) EP3 has to communicate with EP2, it will go through switch. But I believe that both EPs CAN'T communicate like this, there should be proper transaction from RC(root complex) via core. If any communication has to happen between two EPs then 1st EP will write on certain MEMORY and other EP will read from that. Please correct me if I am wrong. Thanks

Thank You for this lecture.

Thank you. it great explanation

Thanks for taking time in going into such detail about BAR programming. Encourage you to contribute more such content

Best explanation till now seen simple to complex clearly explained.. thanks so much

15:56 16MB not 8MB

In PCIe Version 1 on a x1 configuration, the maximum data transfer rate is 160 Gbps (2.5GT/s), but only 2 Gbps (250 MB/s) is encoded serial data?

In a single lane, how fast is the data speed? Can the Tx and Rx channels transmit data simultaneously at 2.5 GT/s? Or is the maximum transfer speed only capable on a single channel, Tx or Rx at a given time?

Please sir make a video on PCIe ltssm States

Can you share this PDF as quick reference

Hi sir, does PCIe support daisy chain configuration

Very Informative, thanks!!

Thank you very much .....