PCIe Architecture: Lecture-2

[@kedarpatwardhan3397]

I understand English is not your first language but the effort and detail that you put in the video is commendable.

[@pavlik6]

I was looking for good explanation of pcie for along time. You are the first that done it in very understandable way. Thank you.

[@pcie3823]

Thanks a lot Pavel Shpilberg .

[@deepapatteri3883]

Thank you very much! Your explanation is clear and precise, nothing more or less than needed for the novice

[@harshadesai7128]

Your lectures are just too good,keep going !! waiting for the 3rd lecture :)

[@liamdillon3176]

Quality explaination 👍

[@kapilkharre]

nice video sir. Waiting for next one :)

[@pcie3823]

Thanks Kapil, I will upload soon.

[@AshokKumar-bf8mv]

A big thanks for this video too. waiting for further chapters sire.

[@well7885]

great work, much appreciated. You should definitely post more LECTURES

[@banutameem2039]

Good explanation. Thanks.

[@vandanasalve567]

Very Informative, thanks!!

[@uditpvyas]

Nice lectures Sir. Thanks a lot for sharing your knowledge. Btw if you have any lecture on PCIe protocol flow (or NVMe protocol flow) between Host and device can you please share that too. Like what will happen exactly when SQ doorbell rings or fetch happens or CQ doorbell rings etc

[@sunilkg2491]

Sir your video was very useful to understanding the pcie..thanks for that..please upload the video regarding physical layer with LTSSM..please

[@maddinabalaji]

wonderful explanation

[@sivas8611]

Great sir

[@LL-ot1oj]

'up to 1K words', it should be 1K DW

[@prasadm8441]

Great effort sir. kindly create more videos on driver code walk if possible

[@EGrb2000]

hi, at 29.49, you say that data length (10 bits) can be up to 4096 Byte. But you can identify only up to 1024 byte with 10 bits. Am i wrong? thanks in advance.

[@dhanushkaveti4320]

Hello sir, Thanks for your lectures. Can you explain about ST THP TD, EP fields in TLP header please.?

[@nagaraju-jo7rx]

sir please explain ltssm initialization and training

[@prashanthireddy04]

In case of read request which field of the header specifies the length of the data (like burst length signal in AXI)

[@pcie3823]

Its length field in header. It is 10 bit field. Data length can be upto 1K DW( 4k bytes)

[@nikhilreddy719]

Is the UPHY (universal physical layer) a part of PCIe controller? Aren't the PCIe controller and UPHY layers different?

[@darshansatyamurthy]

can we also have memory write but non posted? And memory read with posted?

[@kapishpotnuru1883]

Hi sir, does PCIe support daisy chain configuration

[@pankajjaiswal5244]

Hello Sir Could you please tell me Architecture diagram of PCIe to Memory (P2M) for Read...?

[@ptharun23]

Thank you sir..

[@shivam4428]

can u provide more on PCIe 5.0 protols working

[@pawan_wagh]

Hi, Please share all the lectures Notes

[@EGrb2000]

hi, please correct me if I am wrong. During initialization, all connected Devices are assigned some address spaces from System Memory. And devices keep this info of memory space at their specific PCIe Configuration Space. Whenever a PCIe configuration cycle is generated, they monitor their dedicated adress block. Is it how it works? If it is so, how is that pCIe configuration cycle generated? thanks

[@baskars8021]

how 1k word becomes 4kbtes @ 6:20

[@testbenchmaker]

Generally a word is considered to be 4 Bytes. So 1K Words becomes 1024x4= 4096 Bytes . The definition of word size may vary

[@baskars8021]

@@testbenchmakerthankyou. Means word size may vary, noted!