FPGA 33 - Game of Pong over HDMI FPGA design
13:30
FPGA 33 - Game of Pong over HDMI FPGA design
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FPGA 32 - Transition-minimized differential signaling (TMDS) 1280x720p @60fps RGB video over HDMI
10:51
FPGA 32 - Transition-minimized differential signaling (TMDS) 1280x720p @60fps RGB video over HDMI
Жыл бұрын
FPGA 31 - Zynq SoC FPGA Data acquisition to SD card (Acquisition / DMA and record to SD card)
8:45
FPGA 31 - Zynq SoC FPGA Data acquisition to SD card (Acquisition / DMA and record to SD card)
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FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory and PL AXI4-Stream FIFO
6:42
FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory and PL AXI4-Stream FIFO
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FPGA 29 - Zynq SoC FPGA XADC application measures on-chip power supply voltages and die temperature
6:10
FPGA 29 - Zynq SoC FPGA XADC application measures on-chip power supply voltages and die temperature
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FPGA 28 - The power of mixed-mode clock manager
6:04
FPGA 28 - The power of mixed-mode clock manager
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FPGA 27 - Zynq SoC FPGA PL interrupts PS to trigger software execution
7:25
FPGA 27 - Zynq SoC FPGA PL interrupts PS to trigger software execution
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FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)
7:52
FPGA 26 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (VHDL)
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FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)
7:51
FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)
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FPGA 24 - DSP FIR Lowpass Filter with VHDL
7:45
FPGA 24 - DSP FIR Lowpass Filter with VHDL
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FPGA 23 - DSP FIR Lowpass Filter with Verilog
7:29
FPGA 23 - DSP FIR Lowpass Filter with Verilog
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FPGA 22 - How to do VHDL parameterization
4:29
FPGA 22 - How to do VHDL parameterization
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FPGA 21 - How to do Verilog parameterization
4:06
FPGA 21 - How to do Verilog parameterization
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FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LED
6:33
FPGA 20 - Build complete Zynq SoC FPGA application for PYNQ-Z1 with software control of AXI GPIO LED
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FPGA 19 - AMD Xilinx VHDL CORDIC Sine/Cosine generator
4:42
FPGA 19 - AMD Xilinx VHDL CORDIC Sine/Cosine generator
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FPGA 18 - AMD Xilinx Verilog CORDIC Sine/Cosine generator
4:18
FPGA 18 - AMD Xilinx Verilog CORDIC Sine/Cosine generator
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FPGA 17 - Intel Altera VHDL CORDIC Sine/Cosine generator
7:06
FPGA 17 - Intel Altera VHDL CORDIC Sine/Cosine generator
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FPGA 16 - Intel Altera Verilog CORDIC Sine/Cosine generator
5:58
FPGA 16 - Intel Altera Verilog CORDIC Sine/Cosine generator
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FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
6:57
FPGA 15 - Xilinx Zynq SoC FPGA Build your first "hello world" program
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FPGA 14 - VHDL Quartus/Questa finite-state machine design
8:35
FPGA 14 - VHDL Quartus/Questa finite-state machine design
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FPGA 13 - Verilog Quartus/Questa finite-state machine design
7:54
FPGA 13 - Verilog Quartus/Questa finite-state machine design
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FPGA 12 - VHDL Vivado finite-state machine design
8:17
FPGA 12 - VHDL Vivado finite-state machine design
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FPGA 11 - Verilog Vivado finite-state machine design
7:47
FPGA 11 - Verilog Vivado finite-state machine design
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FPGA 10 - VHDL Quartus/Questa two's complement fixed-point arithmetic
9:32
FPGA 10 - VHDL Quartus/Questa two's complement fixed-point arithmetic
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FPGA 9 - Verilog Quartus/Questa two's complement fixed-point arithmetic
7:30
FPGA 9 - Verilog Quartus/Questa two's complement fixed-point arithmetic
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FPGA 8 - VHDL Vivado two's complement fixed-point arithmetic
8:15
FPGA 8 - VHDL Vivado two's complement fixed-point arithmetic
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FPGA 7 - Verilog Vivado two's complement fixed-point arithmetic
8:24
FPGA 7 - Verilog Vivado two's complement fixed-point arithmetic
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FPGA 6 - First VHDL Quartus/Questa project for beginners
7:43
FPGA 6 - First VHDL Quartus/Questa project for beginners
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FPGA 5 - First Verilog Quartus/Questa project for beginners
6:16
FPGA 5 - First Verilog Quartus/Questa project for beginners
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Пікірлер
@intercepter18p68
@intercepter18p68 11 күн бұрын
Is it necessary to add a top level file? I have added the PL side logic (write) in the block diagram not in a top level file. It is printing value 0x00 at all the address of BRAM.
@SkyClaudius-wy6pv
@SkyClaudius-wy6pv 14 күн бұрын
I think this video very useful to me, thank you so much!
@lyem654
@lyem654 Ай бұрын
Delete the music please.
@dvirco
@dvirco Ай бұрын
When running implementation using the files on github I get timing errors. Did you also get them ?
@batkang.6268
@batkang.6268 Ай бұрын
Have you find a solution for that ?
@batkang.6268
@batkang.6268 Ай бұрын
I solve the problem with using the 2023.1 version of vivado.
@dcmaj
@dcmaj Ай бұрын
@@batkang.6268 yes, I added an asynchronous fifo between the dma and hdmi module
@mamangdaya6969
@mamangdaya6969 2 ай бұрын
can you do the other trigonometry like tan,cotan,sinh etc?
@corkedminotaur0
@corkedminotaur0 2 ай бұрын
Nice song dude, thanks for the vid
@toheedh
@toheedh 2 ай бұрын
can you upload a tutorial of doing this with only verilog coding
@FPGAPS
@FPGAPS 2 ай бұрын
Great job! we can also use Ramp function + Lookup table (LUT) to generate the Sin & Cos values.
@stephenpeters4393
@stephenpeters4393 2 ай бұрын
Good video. Can you help me what if i am doing this for two number formats eg (1.8.8) and (1.8.0) how can you make them align first before the addition
@HaramiBalak-h2w
@HaramiBalak-h2w 3 ай бұрын
Hey can you make matched filter using verilog code . Can you plz help me . Its not available anywhere on internet
@shwetaj6622
@shwetaj6622 3 ай бұрын
Hi thanks for the video, it was very informative. I have a doubt, can the DMA transfer more data like 4096 bytes? Using XaxiDma_SimpleTransfer.Can we specify the max packet length to be 4096 bytes? Thanks again
@amirchernin7254
@amirchernin7254 3 ай бұрын
Is it a good practice to multiply numbers like that in verilog? I am dealing with some floating point calculations in one of my projects, and I need to calculate the multiplication of two 32 bit numbers. I used a multiplier block that has some latency, and had to do some coding and testbenching to make sure it works properly. I managed to make it work through pipelining the data, but it would be a lot easier to just use "*". But I'm not sure how the synthesizer would do it. I remember once getting time issues for something like that.
@uzoqboyummatov6111
@uzoqboyummatov6111 3 ай бұрын
great video! Thank you for your effort. Could you please comment, how PS can get access to PL-side external nand flash ?
@zeese5_travel
@zeese5_travel 4 ай бұрын
Hi! Where can I download the verilog and c code file?
@AnkitPandey-w8e
@AnkitPandey-w8e 4 ай бұрын
Could you please provide this code
@carysmacintyre8173
@carysmacintyre8173 5 ай бұрын
I cannot seem to run the simulation, the system report is all find but I get a native link error. when I use the ‘analysis and synthesis’ button on the test bench code i get an error in line 26 saying there is a syntax error ‘10500 VHDL syntax error at counter_tb.VHD(26) near text “)”; expecting “(“, or an identifier, or unary operator’. But I am sure there is no difference between the code you have written and what I have written, but overall a super clear and easy to follow vid so thanks
@مصطفىمصطفى-ض8ج5ي
@مصطفىمصطفى-ض8ج5ي 5 ай бұрын
Which ordre of this FILTER ?
@bachur6306
@bachur6306 5 ай бұрын
hey, why do you make 1.3.28 and not 1.2.28 fixed point from multiplying two 1.1.14 and why do you increase the integer part of the number by 1 each time sum index increases? second questions, how do we know that we can only cut the oldest bits at the end? thanks in advance
@kuzeybayer7836
@kuzeybayer7836 5 ай бұрын
cordic_0 is not compiled in library 'xil_defaultlib'
@kuzeybayer7836
@kuzeybayer7836 5 ай бұрын
cordic_0 is not compiled in library 'xil_defaultlib'
@kuzeybayer7836
@kuzeybayer7836 6 ай бұрын
cordic_0 is not compiled in library 'xil_defaultlib'
@kuzeybayer7836
@kuzeybayer7836 6 ай бұрын
cordic_0 is not compiled in library 'xil_defaultlib'
@sbhtkfxph4444
@sbhtkfxph4444 6 ай бұрын
hy, how can i get the coefficient numbers? there is easy way to know them?
@game2money
@game2money 6 ай бұрын
useful to me
@NithinVarghese-zk4vt
@NithinVarghese-zk4vt 6 ай бұрын
can you do a video on read and write in NVME SSD?
@LOCHA-fc3km
@LOCHA-fc3km 7 ай бұрын
You are awesome, keep going
@yanjiahao8772
@yanjiahao8772 7 ай бұрын
Thank you so much, it's the best approach I found so far, really helps me figure out my fir filter design multiplier block, appreciate a lot!
@ngocmanprocoder
@ngocmanprocoder 7 ай бұрын
hi, i have a question, and I need your assistance. When does DMA stop reading? Many thanks.
@17charles5
@17charles5 7 ай бұрын
搖旗倒讃 高歌離席
@JamesLee-ub4rm
@JamesLee-ub4rm 7 ай бұрын
超爛
@pauleyermann651
@pauleyermann651 8 ай бұрын
If you want the video to be useful please remove that stupid music and click around more slowly
@adelynul
@adelynul 8 ай бұрын
Music name?
@muhammedalikaya268
@muhammedalikaya268 8 ай бұрын
Thanks sir, I want to show a picture on the HDMI monitor. For this, I load the image data from block ram as a coe file. Would it be enough if I use the tmds_encode, tmds_oserdes and hdmi_transmit modules as you did to do the HDMI part?
@GauravKatiyar-yi8ro
@GauravKatiyar-yi8ro 8 ай бұрын
fir_tb.v module fir_tb(); localparam CORDIC_CLK_PERIOD = 1250; // Clock period for the CORDIC at 800 Hz localparam FIR_CLK_PERIOD = 1250; // Clock period for the FIR filter at 800 Hz localparam signed [15:0] PI_POS = 16'h6488; // Positive PI constant localparam signed [15:0] PI_NEG = 16'h9878; // Negative PI constant localparam PHASE_INC_150HZ = 122; // Phase increment for 150 Hz signal at 800 Hz localparam PHASE_INC_400HZ = 326; // Phase increment for 400 Hz signal at 800 Hz reg cordic_clk = 1'b0; reg fir_clk = 1'b0; reg phase_tvalid = 1'b0; reg signed [15:0] phase_150Hz = 0; reg signed [15:0] phase_400Hz = 0; wire sincos_150Hz_tvalid; wire signed [15:0] sin_150Hz, cos_150Hz; wire sincos_400Hz_tvalid; wire signed [15:0] sin_400Hz, cos_400Hz; reg signed [15:0] noisy_signal = 0; wire signed [15:0] filtered_signal; // Instantiate CORDIC for 150 Hz sine wave generation // Ensure cordic_0 is defined or imported in your project cordic_0 cordic_inst_150Hz( .aclk(cordic_clk), .s_axis_phase_tvalid(phase_tvalid), .s_axis_phase_tdata(phase_150Hz), .m_axis_dout_tvalid(sincos_150Hz_tvalid), .m_axis_dout_tdata({sin_150Hz, cos_150Hz}) ); // Instantiate CORDIC for 400 Hz sine wave generation cordic_0 cordic_inst_400Hz( .aclk(cordic_clk), .s_axis_phase_tvalid(phase_tvalid), .s_axis_phase_tdata(phase_400Hz), .m_axis_dout_tvalid(sincos_400Hz_tvalid), .m_axis_dout_tdata({sin_400Hz, cos_400Hz}) ); // Phase sweep for 150 Hz and 400 Hz sine wave generation always @(posedge cordic_clk) begin phase_tvalid <= 1'b1; // Update phase for 150 Hz sine wave if (phase_150Hz + PHASE_INC_150HZ < PI_POS) begin phase_150Hz <= phase_150Hz + PHASE_INC_150HZ; end else begin phase_150Hz <= PI_NEG + (phase_150Hz + PHASE_INC_150HZ - PI_POS); end // Update phase for 400 Hz sine wave if (phase_400Hz + PHASE_INC_400HZ < PI_POS) begin phase_400Hz <= phase_400Hz + PHASE_INC_400HZ; end else begin phase_400Hz <= PI_NEG + (phase_400Hz + PHASE_INC_400HZ - PI_POS); end end // Create 800 Hz Cordic clock always begin #(CORDIC_CLK_PERIOD / 2) cordic_clk = ~cordic_clk; end // Create 800 Hz FIR clock always begin #(FIR_CLK_PERIOD / 2) fir_clk = ~fir_clk; end // Generate the noisy signal by mixing 150 Hz and 400 Hz sine waves always @(posedge fir_clk) begin noisy_signal <= (sin_150Hz + sin_400Hz) >>> 1; // Average the sum of 150 Hz and 400 Hz sine waves end // Instantiate the 5-tap FIR filter module // Ensure fir_5tap is properly defined and imported in your project fir fir_5tap( .clk(fir_clk), .noisy_signal(noisy_signal), .filtered_signal(filtered_signal) ); endmodule
@SsDinesh-t2w
@SsDinesh-t2w 8 ай бұрын
Code is not running
@rav2n
@rav2n 8 ай бұрын
could the design be shared? maybe tcl
@edward4061
@edward4061 9 ай бұрын
Hi thanks for the tutorial. What changes i have to do if i want to send data from PL AXI SPI to PS DDR3 using DMA
@theoryandapplication7197
@theoryandapplication7197 9 ай бұрын
thank you sir
@ArjunRam-pr5yb
@ArjunRam-pr5yb 9 ай бұрын
please can you tell how its actually cofficient convert into hexadecimal value? it will be very help for me
@Serinebey13
@Serinebey13 9 ай бұрын
You're a legend! I've watched numerous tutorials, but when it comes to the test bench, you're the only one who writes the code from scratch. Major respect!
@donaldkelly3016
@donaldkelly3016 9 ай бұрын
When I build and debug as hardware, exit.c opens breakpoints at line16 and has unresolved inclusion of unistd.h commenting out sections of exit.c or entirety of exit.c does not resolve. exit.c is pausing the program right after successful print of "Zynq SoC acquisition to SD card", so right before initialization of drivers or at the initialization of the first driver. It appears that the initialization of the GPIO driver is maybe failing. I was getting following warning for XAxiDma_SimpleTransfer: passing argument 2 of 'XAxiDma_SimpleTransfer' makes integer from pointer without a cast [-Wint-conversion] I also had to change byte written to a UINT. Looks like XAxiDMA_SimpleTransfer wants a pointer, not an array for the 2nd argument. I the warning goes away when you dereference buf_acq_to_dma by passing "*buf_acq_to_dma" xilinx.github.io/embeddedsw.github.io/axidma/doc/html/api/group___a_x_i_d_m_a.html#ga32ca6099d7926297a4c17cdb4a19511b
@tl.nguyen.27
@tl.nguyen.27 9 ай бұрын
Can I ask how to convert -91.75 to 16'h A440?
@vinisharamkumar4181
@vinisharamkumar4181 9 ай бұрын
The number representation followed is signed 2's complement. So the msb bit represents the sign For negative number sign bit is 1 and the remaining bits will be a 2s complete. A and B is 16 bit, and fractional value is 8 bit long and integer value is 8 bit long 1. Convert A440 to binary 1010010001000000 2. The msb denotes it's a negative number .so take 2s completement of the remaining number. 3. Be careful while considering the decimal point
@shravanilakhote7338
@shravanilakhote7338 9 ай бұрын
Sir , is it okay to store the data in the bram using .coe file ? and how do you read the contents of the memory without using hardware ? is there any specific tcl command for that or i can read it through simulation ?
@알바트로스-r1p
@알바트로스-r1p 9 ай бұрын
XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR variable is auto generation????
@AnastasiosAntoniou-e6h
@AnastasiosAntoniou-e6h 10 ай бұрын
I would change the respective part of the code to this: begin phase_tvalid <= 1'b1; if ($signed(phase) + $signed(PHASE_INC) < $signed(PI_POS)) begin phase <= phase + PHASE_INC; end else begin phase <= PI_NEG; end end
@dillanrainerpereira806
@dillanrainerpereira806 10 ай бұрын
Thank You
@GauravKatiyar-yi8ro
@GauravKatiyar-yi8ro 8 ай бұрын
module fir_tb(); localparam CORDIC_CLK_PERIOD = 1250; // Clock period for the CORDIC at 800 Hz localparam FIR_CLK_PERIOD = 1250; // Clock period for the FIR filter at 800 Hz localparam signed [15:0] PI_POS = 16'h6488; // Positive PI constant localparam signed [15:0] PI_NEG = 16'h9878; // Negative PI constant localparam PHASE_INC_150HZ = 122; // Phase increment for 150 Hz signal at 800 Hz localparam PHASE_INC_400HZ = 326; // Phase increment for 400 Hz signal at 800 Hz reg cordic_clk = 1'b0; reg fir_clk = 1'b0; reg phase_tvalid = 1'b0; reg signed [15:0] phase_150Hz = 0; reg signed [15:0] phase_400Hz = 0; wire sincos_150Hz_tvalid; wire signed [15:0] sin_150Hz, cos_150Hz; wire sincos_400Hz_tvalid; wire signed [15:0] sin_400Hz, cos_400Hz; reg signed [15:0] noisy_signal = 0; wire signed [15:0] filtered_signal; // Instantiate CORDIC for 150 Hz sine wave generation // Ensure cordic_0 is defined or imported in your project cordic_0 cordic_inst_150Hz( .aclk(cordic_clk), .s_axis_phase_tvalid(phase_tvalid), .s_axis_phase_tdata(phase_150Hz), .m_axis_dout_tvalid(sincos_150Hz_tvalid), .m_axis_dout_tdata({sin_150Hz, cos_150Hz}) ); // Instantiate CORDIC for 400 Hz sine wave generation cordic_0 cordic_inst_400Hz( .aclk(cordic_clk), .s_axis_phase_tvalid(phase_tvalid), .s_axis_phase_tdata(phase_400Hz), .m_axis_dout_tvalid(sincos_400Hz_tvalid), .m_axis_dout_tdata({sin_400Hz, cos_400Hz}) ); // Phase sweep for 150 Hz and 400 Hz sine wave generation always @(posedge cordic_clk) begin phase_tvalid <= 1'b1; // Update phase for 150 Hz sine wave if (phase_150Hz + PHASE_INC_150HZ < PI_POS) begin phase_150Hz <= phase_150Hz + PHASE_INC_150HZ; end else begin phase_150Hz <= PI_NEG + (phase_150Hz + PHASE_INC_150HZ - PI_POS); end // Update phase for 400 Hz sine wave if (phase_400Hz + PHASE_INC_400HZ < PI_POS) begin phase_400Hz <= phase_400Hz + PHASE_INC_400HZ; end else begin phase_400Hz <= PI_NEG + (phase_400Hz + PHASE_INC_400HZ - PI_POS); end end // Create 800 Hz Cordic clock always begin #(CORDIC_CLK_PERIOD / 2) cordic_clk = ~cordic_clk; end // Create 800 Hz FIR clock always begin #(FIR_CLK_PERIOD / 2) fir_clk = ~fir_clk; end // Generate the noisy signal by mixing 150 Hz and 400 Hz sine waves always @(posedge fir_clk) begin noisy_signal <= (sin_150Hz + sin_400Hz) >>> 1; // Average the sum of 150 Hz and 400 Hz sine waves end // Instantiate the 5-tap FIR filter module // Ensure fir_5tap is properly defined and imported in your project fir fir_5tap( .clk(fir_clk), .noisy_signal(noisy_signal), .filtered_signal(filtered_signal) ); endmodule
@sw3916
@sw3916 10 ай бұрын
Hi thanks for the video, dont you need to connect the fixed_io and DDR pins of the Zynq7 block in the PL via the auto connect?
@yianni28
@yianni28 Ай бұрын
I am thinking the same thing. I followed this video for the Arty Z7-20 and I can program the FPGA but when I go to debug the application I get the error: "Error while launching program: Cannot reset APU. APB AP transaction error, DAP status 0xF0000021" Am trying again but this time after connecting the fixed_io and DDR pins via automation
@yianni28
@yianni28 Ай бұрын
Update: Using Vivado 2024.1 Everything was resolved after I power cycled my board
@alneidit3760
@alneidit3760 10 ай бұрын
Bro pls upload the code bro
@bhavanar6501
@bhavanar6501 10 ай бұрын
can u send the code please
@jonggeunlim6151
@jonggeunlim6151 10 ай бұрын
Nice video