I encounter the error "Error: Computer_Slave_0: Computer_Slave does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis. " as generating testbench from flatform designer for simulation. Computer_Slave is a module I added into system, and other modules added that have similar error. Help me fix it. Thank you so much
@terrycarpenter473310 ай бұрын
Wow for a 5 year old video, sir that was very good, it helped me a lot. The only problem that I had was the audio volume was too low, but not a big issue. I did have some issues with Quartus Prime switching from ??? to WSL to create the make file. I had to load in some Ubuntu update to my Windows 11 system. Also, I'm using a DE0 Nano which has a different FPGA than the one you used. I had some pinout mistakes that were causing problems. I also didn't get the reset and clock hooked up right initially. Anyway... I did get the "Hello from Nios II!" message from my hardware, finally! So, I'm happy for now. Thanks a lot.
@lakshmitejaswi2823 Жыл бұрын
Sir during IO assignments, you have added a csv file. How to add/write IO pins into that file. Plz show the contents of that file. Can you pin it here for reference
@mahendrapratapsingh8986 Жыл бұрын
hi can anyone pls let me know how can i download this tool for further analysis
@Nipulpatel143 Жыл бұрын
Thanks guru, amazing explanation ☺️ What the solution? And here 1 type bug is delay ,but what are others?
@varmavams7402 Жыл бұрын
Hello sir, I got the same error while invoking my SDC file..how you changed sir
@shabbirahammed45962 жыл бұрын
nice...
@vlsikr2 жыл бұрын
TQVM
@AVINASHKUMAR-yd1gp2 жыл бұрын
Isn't it a Mod 16 counter, johnson counter counts 2*no. of flops
@JJ-oo3pg3 жыл бұрын
Too much noise and not clear voice, thank you
@tienvule86593 жыл бұрын
Can i find link dowload where?
@sachinsachdeva97813 жыл бұрын
Hello @siva , Sir i am getting the same error as you got at 03:15. How have you resolved that?
@carterlee2873 жыл бұрын
Really great!
@sitcom_short3 жыл бұрын
see : kzbin.info/www/bejne/a2aTe36nmNpsm5o
@jeswanthreddy4143 жыл бұрын
How do debug in gls
@rahulrajkashyap95303 жыл бұрын
wonderfull work sir...keep doind the novel work
@-PawanKumarS3 жыл бұрын
I installed but after installing only I Downloaded Device files.. how to install Device files after installation
@amisaraaah4 жыл бұрын
Thank you sir
@travelwala25314 жыл бұрын
Sir, I'm unable to install it in my windows 7..please help
@vinayakpatil66214 жыл бұрын
Could you please make some training videos on Cadence tools?
@Santoshkumar-lw1gf4 жыл бұрын
VLSI backend TOOLS for SYSNTHESIS, STA,PnR are possible ?
@GoracyKanal4 жыл бұрын
You are my hero bro!
@shubham7094 жыл бұрын
Thank you very much Sir for this amazing tutorial, by far the best I have come across so far. Only suggestion is, if you are planning to do more such tutorials, which I hope is the case, can you please increase the audio volume? Thanks a lot again.
@AjitKumar-ki5st4 жыл бұрын
sir how to reduce max violation plz tell
@ranchu70835 жыл бұрын
Thank you, But how did you get the "hello from nios" for the 3rd and 4th times ? by reset ? but you did not burn the application into flash! Thanks
@StayInBliss5 жыл бұрын
sir, when you r giving next....how to modify using eco file in ICC
@StayInBliss5 жыл бұрын
pls give some more on prime time tool
@haideralisiddiquee74375 жыл бұрын
Hey, can you tell me from where you got those library .lib, .db, and .sdc
@mystricriver81505 жыл бұрын
HI I want to ask how did solve this Error: Nothing matched for clock_name (SEL-005). I am facing the same error
@carterlee2873 жыл бұрын
I'm also curious
@varmavams7402 Жыл бұрын
I got same.. solution?
@bratislavmarkovic86255 жыл бұрын
Hi Siva! I'm using Altera MAX10 NEEK board and have some issues with downloading the program into MAX10 NEEK board. The target hardware does not respond and fails to print out "Hello world" on the Nios II console. "Downloading ELF process failed" is the message that I get. Do you have any idea what the problem may be? Thanks in advance!
@terrycarpenter473310 ай бұрын
I got the same message, but, when I configured the clock and reset pins correctly... that message went away. For me, that message was saying "JTAG is not working because there is no clock signal?". (I know, I'm answering a 4 year old question and that you probably don't care anymore.)
@hrnbrain8 ай бұрын
@@terrycarpenter4733 I have a De0-Nano, and got the same error and was looking for some answers. Now that I found this solution of yours, I will try it. I will write again after trying.
@yuvarajum52655 жыл бұрын
thank you sir
@ajinkyakautikwar15725 жыл бұрын
Thank You Sir.
@anandjbhatt5 жыл бұрын
Good explanation
@gauravsharma-dy7gs6 жыл бұрын
And after getting sdf delay in vcs flow how we calculate actual delay of cells from library that matches with sdf of gatelevel netlist file
@Fansuri856 жыл бұрын
Thanks, you've just helped me running my project's gatelevel simulation
@gauravsharma-dy7gs6 жыл бұрын
Sir can u tell me without giving sdf file with netlist file to vcs how we get delay in our output?
@Fansuri856 жыл бұрын
I believe the delays are from the saed90nm verilog simulation library
@intelpdk18a6 жыл бұрын
Can you tell where would I get this saed90nm_typ_ht.db file?
@veereshsb72213 жыл бұрын
It's found in data file where your design is located