Very good video sir

nice

I encounter the error "Error: Computer_Slave_0: Computer_Slave does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis. " as generating testbench from flatform designer for simulation. Computer_Slave is a module I added into system, and other modules added that have similar error. Help me fix it. Thank you so much

Wow for a 5 year old video, sir that was very good, it helped me a lot. The only problem that I had was the audio volume was too low, but not a big issue. I did have some issues with Quartus Prime switching from ??? to WSL to create the make file. I had to load in some Ubuntu update to my Windows 11 system. Also, I'm using a DE0 Nano which has a different FPGA than the one you used. I had some pinout mistakes that were causing problems. I also didn't get the reset and clock hooked up right initially. Anyway... I did get the "Hello from Nios II!" message from my hardware, finally! So, I'm happy for now. Thanks a lot.

Sir during IO assignments, you have added a csv file. How to add/write IO pins into that file. Plz show the contents of that file. Can you pin it here for reference

hi can anyone pls let me know how can i download this tool for further analysis

Thanks guru, amazing explanation ☺️ What the solution? And here 1 type bug is delay ,but what are others?

Hello sir, I got the same error while invoking my SDC file..how you changed sir

nice...

TQVM

Isn't it a Mod 16 counter, johnson counter counts 2*no. of flops

Too much noise and not clear voice, thank you

Can i find link dowload where?

Hello @siva , Sir i am getting the same error as you got at 03:15. How have you resolved that?

Really great!

see : kzbin.info/www/bejne/a2aTe36nmNpsm5o

How do debug in gls

wonderfull work sir...keep doind the novel work

I installed but after installing only I Downloaded Device files.. how to install Device files after installation

Thank you sir

Sir, I'm unable to install it in my windows 7..please help

Could you please make some training videos on Cadence tools?

VLSI backend TOOLS for SYSNTHESIS, STA,PnR are possible ?

You are my hero bro!

Thank you very much Sir for this amazing tutorial, by far the best I have come across so far. Only suggestion is, if you are planning to do more such tutorials, which I hope is the case, can you please increase the audio volume? Thanks a lot again.

sir how to reduce max violation plz tell

Thank you, But how did you get the "hello from nios" for the 3rd and 4th times ? by reset ? but you did not burn the application into flash! Thanks

sir, when you r giving next....how to modify using eco file in ICC

pls give some more on prime time tool

Hey, can you tell me from where you got those library .lib, .db, and .sdc

HI I want to ask how did solve this Error: Nothing matched for clock_name (SEL-005). I am facing the same error

Hi Siva! I'm using Altera MAX10 NEEK board and have some issues with downloading the program into MAX10 NEEK board. The target hardware does not respond and fails to print out "Hello world" on the Nios II console. "Downloading ELF process failed" is the message that I get. Do you have any idea what the problem may be? Thanks in advance!

thank you sir

Thank You Sir.

Good explanation

And after getting sdf delay in vcs flow how we calculate actual delay of cells from library that matches with sdf of gatelevel netlist file

Thanks, you've just helped me running my project's gatelevel simulation

Sir can u tell me without giving sdf file with netlist file to vcs how we get delay in our output?

Can you tell where would I get this saed90nm_typ_ht.db file?

Good teaching