Timing Analysis using Prime Time

[@sachinsachdeva9781]

Hello @siva , Sir i am getting the same error as you got at 03:15. How have you resolved that?

[@rahulrajkashyap9530]

wonderfull work sir...keep doind the novel work

[@vinayakpatil6621]

Could you please make some training videos on Cadence tools?

[@carterlee287]

Really great!

[@anandjbhatt]

Good explanation

[@mahendrapratapsingh8986]

hi can anyone pls let me know how can i download this tool for further analysis

[@AVINASHKUMAR-yd1gp]

Isn't it a Mod 16 counter, johnson counter counts 2*no. of flops

[@mystricriver8150]

HI I want to ask how did solve this Error: Nothing matched for clock_name (SEL-005). I am facing the same error

[@carterlee287]

I'm also curious

[@varmavams7402]

I got same.. solution?

[@varmavams7402]

Hello sir, I got the same error while invoking my SDC file..how you changed sir

[@StayInBliss]

pls give some more on prime time tool

[@StayInBliss]

sir, when you r giving next....how to modify using eco file in ICC

[@vlsikr]

TQVM

[@shelendra7782]

nice

[@haideralisiddiquee7437]

Hey, can you tell me from where you got those library .lib, .db, and .sdc

[@veereshsb7221]

From .lib And .SDC from synthesis team .db from top level SoC team

[@intelpdk18a]

Can you tell where would I get this saed90nm_typ_ht.db file?

[@veereshsb7221]

It's found in data file where your design is located

[@AjitKumar-ki5st]

sir how to reduce max violation plz tell