do we need to do monte carlo at nominal corner only?

Why you didn't use npn transistor?

your tutorials are so helpful. thanks a lot.

Sir, which nm model is being used for bjt? Any specific size is to be selected? Why cant we use mos instead of bjt for this? thanks in advance

sir please keep making such videos !

it would be very helpful if you share also the startup design video

I have some doubts related to analysis . Firstly in the formula of fT its Cgs and not Cgg but here we have taken Cgg Secondly , I performed the exact same steps as in the video but still my max fT was around 40GHz but in this video its around 25-26GHz

For finding Vthn and Vthp, you used the Iref=50u, for NMOS and PMOS diode connected circuit, but for NMOS and PMOS it is Iref/2=25u. Why you used total Iref current for finding Vthn and Vthp, after for finding (W/L) you used the correct 25u but substituted the Vthn and Vthp derived from the total Iref value. Why it is like that?

best tutorial with simple examples !

Process corners literally ! Great Lecture

great video!!!

What is the phase margin for the above circuit?

Sir , I am getting error as can't access file 😢 help me sir

great explanation

when in=0.8 all are in saturation but in=1.6 M1 and M2 goes to triode region. Can't solve this.Help me sir.

thank you

Nice explanation

VERY HELPFUL;

Oh my god handcraft layout drawing

Hello sir I got good understanding about BGR.. One question I have to ask will I replace BJT with p or n type MOSFET?? If yes then what will be the size??

sir please .......also make some videos on LDO

Sir,can you please tell us where we can find the pnp transistor you were using.

Really good explanation, thanks!

Thank you so much sir❤❤❤❤❤❤❤❤❤❤

COULD U SEND VIDEO ...HO W TO DESIGN STEPS OP-AMP

Why you are giving input to one of the mosfet only in ac analysis For differential amplifier same should be given in 180 degree phase to another one also naa. Correct me if i am wrong

Hi sir, will u plz do a video on 'worst case corner analysis', else plz refer me whr i can get document of procedure to do it.

5:00

4:02....what do you mean by swing when you say pmos has more swing

Much appreciated sir 😊

Thank you for your great playlist, but you have forgotten the design of buffer stage for opamp as you mentioned in your videos, please complete that stage as soon as you can. Also you can try other structures of opamp too, because your explains are well.

Sir , thankyou this was very helpful Sir can you tell us how we can plot Cgs vs Vgs for nmoscap varactor? Thanks in advance

Either this software is dead slow or you need a new computer ... 😀

sir, I have a module that I have created with the help of Mosfet but now I want to plot the resistance of my entire module from the input port but here I am using the sp parameter method to get this plot while using the sp parameter i am applying pulse input as my module resistance changes with the number of pulses applied to it so I want to plot the real-time resistance of my module as it changes with time as it is a function of the number of pulses applied so with sp parameter I am unable to get this plot can you suggest any method where I could plot this

개지리네 ㅋㅋㅋ

Hello sir, to find W/L ratio of transistor M3 and M4 we went through simulation and for M1 and M2 we are going through different approach(using transconductance),why we can't go by same approach like M3 and M4. plz clear it

Hello Sir, thanks for the tutorial. In the "Virtuoso Layout XL Editing" Window, I can select and move transistors, as needed. But", I face challenges with electrical connections, specifically wires, as I am unable to select or edit them. I would appreciate guidance on how to solve this problem.

Can you help me in my project!

Please share the video on monte carlo analysis of finfet based sram using cadence

Great video

cadence sucks... i was thinking this overpriced SW has at least some rubber-wires like KiCAD or protel98... it is really ridiculous, how can You layout more then a few parts like this?

sir please upload the ocean script to plot gm and id in cadence

I hav done simulation of CTAT & PTAT Ckts in 40nm , but the same circuits simulation I have tried in 16nm with using pnp_mac in cadence tool, but without any circuit change it always showing fatal error.

in general we are not allowed to change channel length n? so for increasing ro there should be some alternate approach ?

I enjoyed these series a lot

thank you sir you explained very well

thank you sir you explained very well

it was a great series of tutorial videos on BGRs, I am personally grateful to you for your efforts Mr. Hafeez!

How do we consider noise parameter or minimization of noise using gm/id technique? please give an example so that we can implement it.

Can we do process corners and process variations for only some of the MOSFETS in the whole designed circuit