Great! This course is exactly for people like you. Either coming from top-down (i.e., software --> hardware) or bottom-up (hardware --> software), it is supposed to connect the dots.

That is an important question, but the answer is actually kind of simple. The LVS flow that I am explaining here is not comparing the RTL or the post synthesis netlist to the layout, because these two things are not equivalent. As you said, they have additional buffers and whatnot that are added to the design - do not change the functionality - but are undoubtedly electrically different. What this LVS flow is doing is to compare the SIGNOFF netlist with the SIGNOFF layout. These should trivially be the same, since you would generally be producing them from the same tool (e.g., Innovus or Fusion). But they may not be because the implementation tool uses abstracts (.lef files) to be able to run with high enough performance. And sometimes this leads to errors. (note, there probably are many other reasons, but this is kind of the high level primary reason). So we are comparing the design AFTER inserting all the buffers and whatnot. I hope that clarifies it.

@AdiTeman Thank you so much for reply Sir. Just for further clarification, at what stage we are comparing our signoff netlist / layout netlist with RTL netlist/synthesized netlist ( Golden netlist ). Though they are functionally the same, how do we validate it.

You're very welcome! So glad to hear!

No, no, no - it is unequivocally "IN"dependent. Synthesis ultimately does map the design into standard cells, which are technology dependent. But on the way, it maps the logic into "primitives" (i.e., AND, NOT, OR, XOR, etc.) which are technology independent. This is what the answer was referring to.

You're very welcome!

Thank you! Indeed, Cadence asked me if they could link to my DVD lectures, and now provide my course as "Digital Design and Signoff Academic Curriculum v1.0". I also had the pleasure to travel to Bangalore a few months ago and teach the course to around 50 Indian professors in a "TTT" (Teach the Trainer) course. Here is a short piece about it: engineering.biu.ac.il/en/node/13341

Not exactly. What you said about dual port is correct (also called "2RW") but the two port allows an independent write and read simultaneously but not two reads or two writes (also called "1R1W". However, it is a little "nitpicking" to make this differentiation, as engineers - and possibly vendors - will actually use the two terms interchangeably. I'll tell you the truth, I have a hard time remembering which is which, so really using the 2RW vs 1R1W terminology is much more clear.

​@@AdiTeman Why can we not do two reads from dual port? Isn't it possible to read from RWL in one cell and from RWWL in another cell?

I love it! 🍕🍕🍕

Microcode is used heavily in CISC processors (or possibly in RISC processors with complex extensions), and yes - it is used in x86 processors today. It is basically a breakdown of the complex instruction into smaller instructions (RISC-style) that can run at the high speed of the CPU. So if I have a really complex instruction that cannot run in a single cycle without creating a huge latency, the instruction will be broken down into a sequence of smaller instructions that can be run at the same rate as other simple instructions in the pipeline. The microcode is usually hard-coded, i.e., it's either synthesized and cannot be modified or is "somewhat programmable" through a ROM or PROM type of interface.

@AdiTeman professor thanks a lot for taking time to answer this, I am learning lot from your lectures. In current world where everything is charged thanks for providing cutting edge knowledge for free and answering questions

Thank you!

Thank you! Check out the new hands on demos that I started uploading yesterday that go along with this course.

You're welcome. Yes, I plan to provide a github link to them. However, I have to "clean" the scripts from any IP, so it will take a while until I have the time to do this properly. Possibly there will also be a version with an open source PDK in the future. Keep posted and I will announce when I finish this series and release the scripts.

@@AdiTeman Thank you. I also took your digital flow course on Cadence website.

Glad you're enjoying it!

Good question, maybe you understood the answer when you watched the rest of the lecture parts, but if not, I will clarify. The Maze Routing, as it is shown here, is very crude. It doesn't take into account all of the very complex features of modern VLSI routing, such as design rules, number of metal layers, etc. The basic idea is that we provide "global routing", which basically maze routes the nets and provides track assignment and then only later provide "detailed routing", which connects the nets according to all constraints. So at the very high level of the grids over here, we really need to only know if there is room to route across this grid cell, and that is usually a function of the number of tracks available vs. those that have already been used (i.e., congestion). During detailed route, the maze routing will be a much smaller scale problem (we're only routing a single GBOX) but with a much more complicated design space, so it will be a bit different.

That is very true. Interesting that it took so long for someone to point out this mistake :). I've added it to Errata in the pinned comment. Thanks!

Yes, that is the meaning. We need to provide both the source of the power (i.e., VDD) and the return path (i.e., GND).

@AdiTeman is it even possible to not provide the return path. Where would the current flow then?

Thanks for the question. This is indeed a good one. There are several reasons for blocking routing, but to give you a few examples: 1) Leaving a "feedthrough" channel for a signal to be routed from the toplevel. Say there is an analog input that needs to be fed from a pad to a block that is blocked by this macro, then we can leave a channel to route the signal when the toplevel routing is applied. 2) Special circuits (usually analog) that don't want to have noisy digital signals running on top of them. 3) A hierarchical macro is only provided a certain number of metals to use (the rest being allocated to the top level). In this case, you would set an attribute for top level routing, but you could also apply a blockage to be sure the tool didn't do anything funny (which these tools are known to do). I'm sure there are many more examples, but these just came off the top of my head.

@@AdiTeman thanks for the clarification

Hi, sorry for my belated answer. The main reason would just be to get them as close as possible to the source of the power supply (i.e., power pad), so the IR Drop would have minimal effect.

Glad you are enjoying it!

So I'm not sure I'm answering the exact question you're asking, but I'll try. The power to the chip comes in from outside the chip (usually). There is a power supply or battery on the board with regulators that bring the voltage down to the DC voltage required by the chip. These are connected through pads to the chip (see the later lecture on I/Os and packages) and from there are connected to the power rings. That is at the full chip level. If we are designing a block and not the full chip, then we will have to connect the power rails from the fullchip level to the block power rings and power grid (stripes).

No, in almost all cases, they are fit into a single row. There are certain standard cells that may be put into two rows, but these tend to be complex cells, such as level shifters and possibly some flip flops.

@@AdiTeman Thank you sir. @12:04 But you mentioned standard cells with higher drive strengths have larger widths. How is it possible to fit larger width in a single row??

That is a good question and it is part of a deeper subject, which is CDC. But basically, we can have no timing constraint between the two clock domains. They are asynchronous, which is why we need the synchronizer in the first place. In other words, we have to design our logic to be completely robust to this possibility of the latency being different numbers of clock cycles. You need to ensure that the logic on the capturing side has a long time to capture the signal (much longer than the worst case synchronizer delay) and that it can't accidentally capture a metastable state.

​@@AdiTemanthank you for your reply

Hi, in Lecture 3, when I talk about standard cell libraries. I also may discuss them a bit in the last lecture in the course, about signoff.

Hi, sorry for the late reply and I hope you already found the next lecture. But if not, then I only prepared two lectures so I'm not sure I made a playlist. But you can get to the lectures either through the Short Courses page on the EnICS Labs website (enicslabs.com/short-courses/) or here are the links to the two lectures directly: TCL part 1 (this lecture): kzbin.info/www/bejne/pZDQmYaXaq2EecU TCL part 2: kzbin.info/www/bejne/ipCXc6mda9OjZpo

Hi @Torchl46 - excellent comment. My answer is... sort of. Indeed, there is a lot of work on AI for chip design over the last few years and it's a super interesting domain. The best known work is, indeed, AlphaChip, which kind of kicked this whole field into gear. But it wasn't started in a vacuum and it has been followed by a real ton of great innovation in all fields of chip design. Furthermore, the EDA vendors are also providing AI-driven solutions in their commercial tools. Why do I say "sort of"? Because I have a student who works with the AlphaChip team and has been able to run the tool and evaluate it. But I haven't personally (actually, at this point in my career, I don't get my hands wet with "real engineering" that often...). I will tell you that I ask around quite a bit and I don't find many backend teams in industry working with the new tools yet. I imagine it will come, but it's sometimes hard to steer this very heavy ship that has been moving in one direction for many years ;)

You are very welcome!

Hi. Your confusion comes from me combining two separate phenomena in this example. First, IR drop - here, I just measured the resistance. The resistance is for sure not "irrelevant with width of the rails" because the wider the wire is, the "fewer squares" you have. My best way of explaining this is a highway with cars running on it - the more lanes (width), the more cars can pass at once (current) or in corollary, the lower resistance. The reason we care about resistance is "IR" drop (Ohm's law: V=IR), so we also need the current. If the current is tiny or non-existent, then "who cares" what the resistance is, right? So in the second part of the exercise, I tried to get a representative number for the current to understand if the resistance we calculated is problematic. How do I get such a number? Are we conducting mA, uA, nA, pA? So I used the number for the maximum allowed current, which is defined by EM constraints. For EM, we are also limited by the current density, which is the current divided by the area that the current goes through. Since the thickness of the conductor is given (like in square resistance), we only need a number for current divided by wire width and that is given as 1mA/1um. Since we chose a wire with a width of 100nm, we got a maximum allowed current of 0.1mA. Now, assuming this could be running through the wire (if it's allowed, then we're going to drive it through, right?!), then we can find what the voltage drop is going to be. I hope that cleared it up.

@@AdiTeman thank u somuch! I consider I understand now

Thanks for the kind words. Actually, I am far from an expert on Operating Systems and so am not extremely familiar with the best sources. I put a lot of the books and websites and courses that I used in the references at the end of each lecture, but I got to these through Google searches and such. If I had ChatGPT or similar when I collected these, I would just ask it what the best references are or to just summarize it all for me. I can suggest this (or other chatbots) as a great source!

Good on the spot question. Yes - "column mux" and "column decoder" are the same thing. To be accurate, it is a mux - it is selecting one bitline out of a set of bitlines. The reason the term "decoder" is used is because often the mux is (at least partially) implemented using a decoder, as I explain in the slides.

Hi, Actually, I found this quite a while ago and don't remember exactly where, but as I mentioned in the caption, the source is Fairchild, which is one of the original IC companies (the "father" of Intel, AMD and others). I imagine I found it on Google...

@@AdiTeman ty i will put one of these drawings as a poster on my wall :D

Hi, This is a well known "concept graph". In fact, it has been later claimed "never to have happened". The origin is an analysis by Sematech in the late 90s (e.g., ITRS 1999). You can read about it, for example, here: semiwiki.com/eda/cadence/7622-an-update-on-the-design-productivity-gap/

Much appreciated!

Yes, in general you can. Quartus is a suite for programming FPGAs. It includes the code editor, simulator, synthesizer and FPGA place and route. This is not applicable, however, for ASIC design as it only targets FPGAs. That said, for simulation, it is fine to use Quartus and for synthesis, it will give you an idea of what ASIC synthesis is like.

@@AdiTeman Thank you for your response sir!!

Thanks! Check out the entire course and the rest of my lectures at enicslabs.com/education/