Hi, Yes, this is probably the best order. Thanks for pointing this out. I have a few comments/addendums: 1) SoC101 is probably independent. It could be watched first or in the middle or whatever. 2) The Digital Electronic Circuits lectures are only in Hebrew. I don't teach the course anymore (for many years) and so haven't taken the opportunity to update the course and record it in English. That said, all the content (slides, handouts) are in English and they are quite self explanatory. 3) There is a lot more content, beyond my core courses. At the EnICS Labs website (enicslabs.com/education/ ) there are several categories of lectures, including short courses and tutorials. These are mainly complementary to the core courses and really worth checking out. Thanks again, Adi

Perfect!

Welcome

Hi, Actually, in many ways tcq is independent of tsetup and thold and so there is no answer to your question. In Lecture 7 of my VLSI course, I explain how to construct a general flip flop standard cell and how to calculate these parameters for it, which could remove some of the mystery around this. See this lecture: kzbin.info/www/bejne/j37UY2iYjJKNa8k In any case, each of these parameters is heavily dependent on the circuit design of the underlying block and the values can vary a lot. For the flip flop I show in that lecture, tcq is very short and thold is negative, while tsetup is quite substantial. For other implementations or other circuits (e.g., SRAMs) these relations can be totally different. In addition, process variations (corners) can change the relations between these parameters.

כן, בוודאי שמה שכתבת מדוייק. פליטת פה בהסבר. תודה על תשומת הלב.

@@AdiTeman תודה על ההרצאות המונגשות והמעניינות.

Yes, thank you for pointing that out. Indeed, TI does do some manufacturing in-house, and used to (several decades ago) fabricate all their chips in-house. That said, they are not one of the mainstream foundries that fabless companies usually tape out in, and for sure not making advanced nodes in their fabs, but rather specialty "More than Moore" technologies and older, very mature nodes. The reason I put them in the chip design category (and didn't point them out as a foundry) is that TI still has a large chip design operation that tapes out in advanced nodes using external foundries, such as TSMC.

Yes, of course. These cells have a feedback path (they are basically a bi-stable cross coupled inverter). When we try to overwrite the state inside, we drive a different signal in, but the feedback is resisting this. Therefore, we get a ratioed operation. Since we want this to work flawlessly, the tri-state breaks the feedback loop and ensures that the driven value is not contested and will for sure be written successfully.

Thanks for the kind words!

Just like dynamic logic (you can find explanations in the Digital Electronic Circuits course enicslabs.com/academic-courses/introduction-to-digital-electronic-circuits/ - videos only in Hebrew, but slides in English) a digital decoder can be much faster than CMOS and can be realized with fewer transistors. However, it comes at extra power consumption and more risky implementation.

Thanks! That was 100% my point of making this course (and I personally really love it!)

Hi, Actually, the entire physical design flow is iterative. It is actually iterative in more than one way. The first way of looking at it is that you run each of the steps many times with different parameters and each time you look at the results, analyze them, modify parameters and/or the design and re-run. Another level of iteration is the algorithms themselves, which usually have some optimization flows within that incrementally improve the result until the constraints are met, no improvements are made or a certain amount of time/effort has elapsed. I hope that answers your question.

Hi. No, the tool doesn't "understand" the name of the signal. To the tool, it is just a string. On the other hand, we try to name our signals with meaning and this is one of those examples. In this case, because of the underscore, we can guess or implicitly understand that our reset is active low. In other words, the reset is asserted by pulling rst_ to ground. if we called it "rst" and not "rst_", we could assume that it is active high (i.e., reset is asserted by pulling it to VDD). Other ways you could name an "active low" signal are with an exclamation point (though this is not good practice for computer languages), the word "bar" (e.g., rst_bar), or the letter "b" (e.g., "reset_b" or "resetB"). But, again, these are just strings. You need your code to implement the active low behavior.

Thank you kindly!

Many thanks!

Hi @shinyskystar, I would be happy to receive your CV though I cannot promise anything. You can reach me at [email protected] Adi

@@AdiTeman Ok Sir Thanks a lot

Hi, The easiest thing in my opinion is just to remember the following: "Negative Body Biasing raises VT". For an NMOS, that means that if I put a negative voltage on the bulk, my VT is higher. For a PMOS, the opposite - if the NWELL is biased higher than VDD, the |VT| of the PMOS becomes higher (i.e., the VT becomes more negative). To understand in general, physicists have many ways of explaining things that are all different ways of looking at them. One thing you could try is that there is a certain amount of voltage you need to apply to the gate in order to invert the channel. If I put a negative voltage on the body, I need to apply more voltage on the gate to bring the channel to the same voltage. This can be supported by the two capacitor drawing I show many times in the slides, where the gate-to-channel capacitor is what we want to control the channel, but the channel-to-body (or channel-to-others) capacitance is "fighting" with the gate voltage. If we apply a negative body voltage (on an NMOS), we are effectively increasing the gate-to-body cap and making it harder to invert the channel. Hope that helps...

Hi @FritzKissa - You are 100% correct. I don't know where this error came from. I am pinning a comment with the correction. Thanks!

Hi, Actually, that is not an easy thing. I don't know of any comprehensive textbook that provides everything I cover in this course. That said, there are many books and other material that you can find that together will provide everything. What my main suggestion is, is to look at the list of references at the end of each lecture. I have tried to put the main sources that I relied on (other than my own experience and knowledge), so for each lecture, some relevant text book may be available.

Thank you for the appreciation. I have a lot more content available on KZbin for free, which you can access through my channel or see in a more convenient layout on the EnICS Labs website enicslabs.com/education/ I'd love to hear more feedback and I hope to find time to create more content over the summer.

Hi, Yes, indeed you can pad cells and that will reduce the pin density. Of course, this comes at the cost of extra area, but it could be useful to apply to certain hierarchies. I guess this is the same as applying a lower target utilization, though going at it from "a different direction". As a side note, cell padding is usually used for things like leaving space to put decaps next to flip flops and clock buffers to improve the dI/dt drop near the toggling clocks. But it could be used as you suggested, as well.

Hi, A timing model is a simplification of how to calculate the delay (and a few other things) through a digital gate. This is fully covered in Lecture 3 of this series. Specifically, I suggest you watch this video: kzbin.info/www/bejne/l5ynZZ95ZcmYg80

Hi, So, my intuitive, straightforward answer is that if two nets are routed close to each other for a substantial distance, then there is a good chance that an SI issue will occur. But it's very hard to actually see this without a tool, since you have lots (...millions... billions...) of nets with different segments and so forth. Which is a victim and which is aggressor. Well, first of all, they can "trade places". In other words, one of them can be the aggressor to the other for a certain timing path and can be the victim for a different timing path. But usually, the victim will be the one that is weakly driven, which can be seen as a slow transition on the net. You can look at DRVs - max capacitance and max transition (and max fanout) reports to find high potential candidates for SI problems. But really, just use the tool...

Hi, Thank you so much for the kind words. Indeed, I do not provide any hands on/live material at this time. This is due to commercial restrictions - both of the CAD/EDA tools and of the IP that is used (standard cell libraries). In the future, I may get permission from the two sides and work on providing such material, but this is also really dependent on my time (both to go through the bureaucracy and then to actually go and make the recordings...). And as you can probably see from the amount of material I have uploaded lately, time is something I don't have a lot of. Who knows, maybe things will settle down and I'll find the time (though I have been promising my wife that "I will have more time next month" for about 15 years :).

@@AdiTeman Thank you for the detailed response and for the incredible content you’ve already provided. I completely understand the constraints around commercial restrictions and time commitments. Your lectures have been immensely valuable, and I genuinely appreciate the effort you put into them. I have completed the DVD lecture series and I am going to start with your SoC playlist soon. If you ever do get the chance to navigate the bureaucracy and find the time, a hands-on series would be fantastic. Meanwhile, I’ll continue learning from your existing materials and look forward to any new content you can share. It would be great if you could suggest some online courses or any other references in your knowledge that could help gain this hands on experience before I actually enter the industry. And I hope you manage to find that elusive free time soon :) Thanks again, and best wishes! Regards!

Great to hear! Please give me feedback on my other videos and I'm open to suggestions for more material (though, who knows when I'll find time to record more :)

EDA stands for Electronic Design Automation. This is the general name of the programs used to design chips. We also call them CAD (computer-aided design) tools, but CAD is used in other fields, whereas EDA is usually used for hardware design utilities. I suggest watching my other courses to learn all about this field. You can find my material at enicslabs.com/education/

You are most welcome

All of the slides are available on the EnICS Labs website. The webpage for this course is at: enicslabs.com/academic-courses/dvd-english/

@@AdiTeman thanks for your reply but I cant find the direct link to download it, can you please provide it?

@@thangdaoviet419 No problem. There is a button on the right panel of each lecture that says "Lecture X Slides". For this specific lecture, the link is: www.dropbox.com/scl/fi/d5sqn83htkyifkbed7nfu/Lecture-3-Synthesis-Part-1.pdf?rlkey=e0jfxerycb03brp3feq3q265t&dl=0

@@AdiTeman thank you very much, have a nice day ^^

Thank you! That's what makes me motivated to provide more material (hopefully, I will have time to make some more videos later this year).

You are so welcome. That is what they are there for! Hopefully I will find time to prepare more videos later this year. I have a long queue of lectures waiting to be recorded - I just have to find the free time to get around to it.

Well, I don't know if just watching the videos is enough, but it is a good start!

Yes, you are right. There is an "extra" dx there. Thank you for pointing this out (it "magically" disappeared on the next slide ;)

@@AdiTeman Thank you for the clarification, Professor. I really enjoyed the lecture and appreciate your guidance on this point.

Thanks!

Hi, Sorry that I haven't provided it as of yet. I may be updating the course recordings soon (a lot has changed since 2020...) and maybe then I could add some labs.

Hi. Tough question. These things mostly run on Linux and aren't too friendly for home computers. But you can start by buying a starter FPGA and programming it. The FPGAs come with a tool suite that runs on Windows and you can learn a ton from it (and FPGA design is a very popular and required skill on its own). Try starter kits from Xilinx or Altera.

Hi Haziq, Indeed, this is a really bad naming convention, but I didn't invent it. Maybe I should have changed it, because it's so upside down, but I kept what was in a reference that I based it on. You can see in the bottom figure that the usage of DIN/DOUT is the same (pay attention that the PAD is connecting outside the chip, while the ports are connected to the chip core). I can try to give a makeshift explanation, but really, it is going to be a bad one, because if I were to design these I/Os, I would label the pins in the opposite way. Here it goes - "we are looking at the I/O from the perspective of the other chip, so its outputs are connected to DOUT and its inputs to DIN. Where the other chip is receiving is the RX I/O and where it is transmitting is the TX one". So after we got that horrible explanation out of the way, I will say that these things just depend on whatever the vendor who developed the circuit decided to call it. So you have to read the manual (good luck ;) and adhere to it.

@@AdiTeman well the explanation isn't that horrible. And by not changing it, you saved the students from future confusion. Thanks!

Hi, I guess you could look at it this way, but I think it is more straightforward than that. The solution to the optimization problem is to differentiate the entire system. This is a set of equations that you can collect into matrix notation. The connectivity matrix is basically the outcome of writing down all equations and collecting them together. But the "observation" is that this matrix has features that "are intuitive" and "make sense" and represent the connectivity of the netlist and therefore it's just straightforward to write it down. Note that there is some amazing work by University of Texas (David Pann), where they use deep learning inspired optimization to solve the placement problem ("DreamPlace"). I highly suggest looking into this, because it's really really beautiful.

בקישור יש כפתור ליד כל הרצאה עם קישור למצגת.