SoC 101 - Lecture 8e: Circuit Editing FIB

[@liamvervecken3231]

Great course, thanks for putting in the effort! The real-world example and including some typical struggles at the end was a nice touch.

[@AdiTeman]

Thanks for the kind words!

[@Elior92]

Hi Adi - Loved your course. Thank for that. If you can answer few questions (just out of curiosity) - 1. About the hold violation - so didn't you run all PVT scenarios in signoff or was there just some SDC screening off the violation? 2. Now that you understood the issue with the memory rst, what can you do for mass production? to which layer did you drill inside it? Doesn't that mean you have to reproduce many masks for it (metal fix)? Thanks for this course it was very interesting and helped me a lot!

[@AdiTeman]

Thanks! For the hold violation - we ran regular BC-WC. Had some trouble with licenses and tool setup and ran out of time. We had an "opportunistic tapeout" so preferred to make it on time rather than making sure we took care of everything in signoff. But we figured that with large hold margins, things would be okay... they weren't. For the FIB issue - we actually did several fixes because Maser didn't guarantee that it would work and for a few other reasons. So we had some that went down as far as M4 (in the end, all of the fixes worked!). Regarding mass production and metal fix - in any case, this was a shuttle, so (usually) metal fix is not a real option (though a simple metal fix would have done the job). We had another tapeout coming up in any case (as I mentioned, this one was "opportunistic"), so it was an easy fix before the new tapeout.

[@Elior92]

@@AdiTeman Thanks for the reply. Great to hear that everything went well at the end. Once again, great course and the last lecture about the bring-up really added a good context to everything.

[@AdiTeman]

@@Elior92 Thanks. I think so too. I wasn't expecting to get this additional lecture, but I felt that it fit right in.