Thank you for your session

What type of syringe was used again? I can’t make out what she said to use.

Logical operation first upto 3rd Stroing device SSD nvm2 stroge

interesting....................

Thanks, for the simple introduction to the gas sensor test. Please add some homemade gas sensors.

Thanks for explaining!

What is the advantage of using the Separate ref clock in compare to Data Clocked architecture?

Thank you for the excellent video. In a data clocked topology the receiver must support the full 20ns jitter of pcie spread spectrum clock. I understand this is largely reduced in a common clock topology. However I could not find a number specified. Is it reduced to 10 ns? 1ns? 1ps? Do you maybe have an indication per your experience?

Alcohol will irreversible contaminate some sensors...

Flexic ind. Microelectronics ltd

could you explain exactly what kind of technology progress enables say data rate to double between generation 4 and 5? In other word, what factor limit gen4 data rate to only 16gb/s but gen 5 could reach 32?

Hello. i have a motherboard with a PLL setting at 1.8 volt for pcie/northbridge... should i increase the voltage?

How to improve this?

Nice.

Ma'am how to calculate humidity and pressure sensor response and recovery time what apparatus used to check the responses?

Thanks that is a nice explanation. Thanks for keeping it short.

This is pretty interesting. No we are not related as far as I know. I work in radio. I'm subscribing.

The result assume unterminated transmission lines. If probe input impedance is terminated at 50 ohm, then these plots are incorrect...

my friens name is viresh patel he is veary gangster pls sponsor him

Very interesting. My friend Joseph Rothrock is a huge fan of this video. Even made a shirt with the thumbnail on it

I want to know how the capacitor rating at the load point affects skew/slew in relation to frequency. Some designs call for 0.1uf others 0.001uf. Some don't even use a capacitor.

Hi Ron, Great presentation. But, I would remove the "c" in dBc. This is the closed loop gain of the PLL and is measured in dB not in dBc. We use dBc in the phase noise which is different than what you're showing. Cheers.

do you have the s3p,. CAD file for this product

Is there any way to make a Graphene-iron oxide nanocomposites Gas Sensor that can be used in the method shown?

How does PCIe 4 and 5 transfer compare to DDR4 and future DDR5 DRAM?

thanks

Great. Drop us more like this.

Thank you so much! This is a great tutorial!

How these two parallel 9pF capacitances become 4.5pF?

Is this for PCI express slots on a motherboard, or for M.2 NVM express solid state drives?

Nice explanation. At the measurement point in the circuit diagram, what would be the effect on the CLK signal of having a filter capacitor that's too small or too large?

What if it's a data line? Do we need to put series resistors on both sides of transmission line?

I am building a Schmitt Trigger to clean up the signal on a DIY GPS Timing Reference. I thought that my poor waveform issues were likely related to incorrect termination. So, I watched your short video. It was two minutes of exactly what I needed! I tested the S-T with my function generator. By varying its output resistance (50/600 Ohm button) and adding a variable resistor in series and parallel after the Schmitt Trigger, I was able to effect/improve the waveform's shape. Thank you!

good lesson! thx!

here you are using liquid for testing gas sensor, my question is, how to calculate particular PPM by using liquid

Great video !!! Can you please post the low -level video explaining what is refclock ? Why it is needed ? full explanation of SRIS

How would be the equivalent capacitance of 9pF parallel capacitors gone 4.5pF? please explain?

lol

Im pretty sure my fps will be the same in game whatever i have a gen3 or gen4 PCI express ! Is anothe gimmic !

Regarding 7:10 .. how do you define "low" RMS phase jitter from high RMS phase jitter?

How does one determine where to place the jitter mask to obtain an appropriate phase jitter? What determines how far it should be offest from the carrier frequency?

Hi, can you explain what is role of DQ/DQS in DRAM operation.

Thankyou for such Informative video on PCIe clocking. Looking forward for detailed explanation.

Hoe can we ensure SRIS device is operable on all root ports in PCIe?

can i switch dc? will dc pass?

Can a motherboard with a newer/higher generation downclock to any generation before it? i.e. Can a PCI-E gen 3 x16 motherboard slot downclock to a PCI-E gen 1 x1 card?

Does Anyone know any vehicles that use SENT interface on throttle bodies?

Thank you! Good training!

Hello this is a nice presentation, are the slides available somewhere?