11:05 Sir the delay is not synchronized because if the inverters. How can you say so?

nice sir

really helpful lectures!!

Really very nice Lecture sir ji 🫡🙏

Thank you so much for this huge effort The series is full of information and it is really great to have a complete vision of what VLSI is about Thank you again 🙏

Dog legs was a good one! First time seeing sir laugh :D

where i can find its original version

what is 1.2 in multiplier pipeline power equation ? @13:15

in xor, if two inputs stuck at 0, then these test vectors cnt find stuck at 0. as with all 111 actual input ll be 100 and out put will be 1.

how 690 ohm came ?

can any one tell what is link of multiplier and false path and XOR gate fanout and false path ?. at time 6:15 ...

for small violations and too many vilations ?

is it tool do all these things automatically or we can choose some options ?.

is there some options in the tool, to choose clk distribution network and for specific part of chip ?

22:22 when FC =1, DL=0, not 1

watching 6 year old video bcz tomorrow having exam😅😅

Very useful lecture.. thanks for uploading!

A & B techniques are valid , but A is a subset of B...But the problem is example given in C isn't practical...depending on whether Si or Sj being the initial state the other wouldn't exist

❤

so in CTS spec file we give target skew , is that local skew or global skew ?

What is the tool used for generating test patterns in practical

very helpful! thank you

Sir please send me contact no

The world's best teacher thanks sir

So nice thanks sir

thank you Sir for your good content.

This is for which year in ECE?

The whole series is wonderful. I'm so lucky I stumbled upon these lectures. Dr Sengupta is a GREAT teacher. Not only are the explanations great, but the way he builds up a given topic by explaining what it is and what's its use (before explaining how it's done), deserves special mention.

Lec 63

lec-62

Thank you sir, for great effort

I think Lg is wrong at 18:16

Please shere the PPT also ??

Sir u explained NOR gate schematics for the NAND gate..

Differential Fault Simulation?

Sir why can't you explain in simple words

Thankyou so much sir. Great explanation

@12:40 V0 - V3 it should be W23

sir, that is CMOS NOR gate ... not a NAND gate

Shouldn't the select line for the MUX at 7:56 have a frequency of fref/2 for correct operation?

Thank you so much your teaching style is awesome. Everyone can easily understood

In the fault for MUX shouldn't it be ((La0 ∩ Ls') U (Ls ∩ La1)) U {F/0} to ensure that fault does not occur on the select line when fault occurs on A0 and A0 is selected?

because of you people we student can survive in our colleges ............thankyou so much sir for everything .🤩🤩😊

What are Rint and Rtr in the cascaded buffers section?

Hi sir. I have a question about abutted Floorplanning

thank you sir for your helpful content. this helped a lot in our final year semester exam

Subtitles in Gujarati Language is of some other video.

Thank you very much for your videos

In the nine zone method there seem to be only eight zones. Can someone explain how the ninth zone came?

great video