What facilities are available for wire bonding?

Uh, the title of this video is very misleading; this is 'Altium Improvements to SPICE Simulation in AD22' it is _NOT_ a tutorial on how to simply do SPICE simulation in Altium. The improvements look enticing, but the misleading title is an annoying hindrance causing search engines to lead here when they should connect elsewhere. Even the video description is incorrect: "Learn how to conduct a simple simulation in Altium Designer here." Nope, that is _not_ this video.

The issue here is your reviewing parts that answer schematic. This is the documentation for the product as well it goes into so it’s not really fair to compare this as part of the electronic design as other people will put the documentation separately.

I may be late to this particular party, but what I came to say relates to *everything* you do on this channel. To Altium, or to whomever buys you off, you must be worth your weight in diamonds! Also, please consider a small request, if possible. Please figure out what channel options need to be switched on or off, buttons pressed (or hammered through all 12 layers of this cursed platform) to make your valuable replies to viewers' comments under your videos public. We only see some comments got a reply, but unable to see what you wrote. Greetings from Croatia! Marko

How to free download altium software

At 0:29, you cleared the highlighting of net VCC3. How did you do that? In my designs, ALT+Left click cannot be undone in any way!

Can we use 2 gnd planes in the inner layers (4 layer pcb) ? One dedicated to PGND and the other one to AGND. Both of them are connected via a net tie.

argument is a bit wrong the cs# is needed. during power up, and also power down typically the memory chips are fully powered on at 1.2-1.8 on their way up to to for example 3.3, during this time an SoC for example will have indeterminate state on the I/O, likely floating or small internal pu. it is during this time the cs# pullup will save your memory from an accidental write. It wont happen often, maybe once in a million cycles, but once you make many units you will notice this failure.

This was very informative. Thank you.

Nice - I am double - altium - designer, circuit studio, circuit maker, why 3 tools. ?????????????????? L&T spice for electronics and ansys is different from other simulator. did they use l&t or altium or proteus , lot doubt and confusion. 🥶🥶🥶🥶🥶🥶🥶😵‍💫😵‍💫😵‍💫😵‍💫😵‍💫😵‍💫

As an ASIC engineer I can tell you that if your IC vendor tells you "pulls" are needed, then you should use them. With CMOS inputs you should not leave the pin state at an intermediate level, the pin should either be fully "on" or fully "off", otherwise you end up with potentially significant crossbar currents. The need for "pulls" really are for inputs or inouts (when they are in input mode). Typical ASIC IO libraries have a large selection of IO buffer types for the ASIC team to choose from (or of course they could use a custom IO design). As an ASIC designer I can choose to use input capable buffers that have "no pulls", "pull up" or "pull down" or in some libraries the ability to configure them. For designs reasons that are beyond this discussion the designer may choose to use an input buffer that has no "internal pulls", in this case the local PCB design is required to ensure that the input pins does not float and has a valid input level at all times. A PCB pull resistor does this. However, in the other case where the chip designers has used input buffers with pulls it is a little more complicated, many input buffers that include pulls have one important caveat. They are not to be used to replace the need for "board level" pull resistors. They internal pulls are very weak and intended to ensure the input buffer has a valid input level only when the pin is left disconnected. The behavioural simulation models often even include huge delays in modelling the pulls to avoid designers relying in them. IMHO it is why there seems to be "no consistency" in where SPI connections need pulls or not, in part is is because what other functionality is shared on those pins, can they be configured as inputs, might they be used for undisclosed test or "secret" functionality etc? If you want the definitive answer as to whether a pin requires a pull resistor, ask the chip vendor/designer and follow their advice because they actually know if and why they would be required.

TVS is important for protection from strong RF levels into the LNA, it will be damaged without

Regarding AI trend, when can we expect something similar to Copilot in Altium, so that many routine tasks can be solved by a prompt rather than hours of manual drawing and setting up?

Everyone knows you only need series ferrite beads for SPI bus signals.

Arigatov❤

Many micros boot with their GPIOs defaulting to inputs until the code has a chance to configure them. Therefore the pullup resistor ensures no spurious chip selects or clocks before the processor has a chance to start

I have come to the conclusion that the pull-ups are mostly useful to have a well defined initial state for the SPI bus. This could also be useful for any other pins that are not SPI, but where you want a guaranteed initial state, e.g. one that controls a transistor base/gate or relay. Like you said, for most stateless ICs (like a sensor) this initial state doesn't matter. If the undefined state of the bus magically sends a valid but unknown SPI command, I'm probably just gonna send a reset command to the device during initialization. You didn't touch on the resistor seen between SI and SO signals. That could be useful when interfacing between 3-wire simplex and 4-wire duplex SPI interfaces, though I've never actually done that.

Zach, how to contact you by E-mail? I would like to attach some files and explanation of my problem with Altium? Thanks in advance!

In my opinion, you need resistance for pullups when can do 10+ reps. My simulations for Zach's arms in AWR show that resistance does not work him anymore because he can do 100+ reps. If I add a short ended transmission line and set his pullup frequency right, it will have high reactive impedance and make his workouts challenging, allowing him to progress.

My board turned grey and i can't revert it back to normal. Anyone have an idea how to fix that?

thank you very much Zach, not only teaching smth fruitful but also opening my mind on thinking about circuits.

Have you done any videos on ground reference resistors and bias resistors in analog circuits? I know how to do the maths for these, but today's digital kiddies might benefit from one of your deep dives on the subject.

Most of the time just follow whatever your chip manufacturer suggests. Recently i worked with a PCIE to SPI bridge that required pull ups on some of the SPI lines and would just not work without it.

There was a point made about using the pull-ups in sd-cards or similar disconnectable devices... especially on miso and cs lines to avoid leaving them floating or subject to noise when connected.

no there is no mis match. the induced noise cannot come later because it's from the same source. the noise is on the edge of the lower signal but should subtract in a similar way.

Will this demo go through all the bugs and work-arounds for them? This software should be free until they are fixed (crashing Altium, not updating the images, unable to handle multi-pin connections etc.).

lol, the series begins with, a full circuit (including a rectifier) and "let's do it from scratch..." then half of the circuit just appears, but not gone into every component specification, a bit off explanation here and there, and at the very end the rectifier appears again out of nowhere 😅

Thx for the info. How can we get a hold of the document?

This was helpful, thank you. My license had switched to "viewer only" for some dumb reason.

I regret not taking EE courses at university.

Zach, maybe you should remind for the young channel followers the thumb rule for bga fan-out to number of layers 😉.

Sir as per table collapse bga we do reduction as per solder ball diameter.means pcb pads should be less than solder ball diameter. But in non collapse bga we increase the pcb pad size as per solder ball diameter. We used maximum material condition mmc.but you have mentioned reduction in both the tables . My question is in collapse bga 0.15mm with 15% reduction and in non collapse bga 0.15mm with 15% increase .is it correct

Interesting, but how do you create the components for harness's like a connector

Send Zach your design here: www.linkedin.com/in/zachariah-peterson/

Best classes I ever had!!! Congratultions!!! Zach. Very clear voice and rithm. Videos are full with very usefull information!

Very well put

Altium - thank you for joining!

Watch the Full Interview Here: kzbin.info/www/bejne/j3-6g32Drt2gmpo

"Any terms and conditions of Customer are excluded, irrespective of whether reference is made to them in offers, purchase orders, order confirmations or other documents regardless of whether Company has objected or not. Any prior agreements including but not limited to confidentiality agreements concluded between the Parties shall be in its entirety replaced by this Agreement retroactively as of the execution date that agreements." I think this gives them the right to scam their customers.

I couldn't find any information about Mitai's pricing.

I did my first Altium PCB Layout by taking help of your video. I'm Regular OrCAD PCB Editor (Allegro) Tool User. Thanks for your video Phil.

Could you please explain where exactly these pads type are used?

how is the GB switch project progressing?

Thanks...just the right length and detail of the video!

Kill me. I have as a homework assignment to design a PCB from scratch and I always lose my mind while doing the components footprints 😭😭😭

After going through a turmoil of understanding the exact working principle of DCM operation of flyback converter, I ended up in this amazing explanation. Thank you for such a lucid yet simple explanation. How do we also calculate the core loss and can also verify the BH curve for the same ?

Where can I buy the same T-shirt with the Altium logo? :)

Interesting topic. One important thing missing here is io (connector) protection for over voltage events like surge, burst and esd. Zach mentiones io protection but that is not fully covered, but probably easy to implement with an AI rule.

Etch tolerance is very critical on these boards as the patch dimensions should be as close as possible to the intended size. Always ask you PCB vendor to send measurements of the finished etched antenna array. Stay away from Rogers 3003 as it is very difficult to work with. And watch for the unbalanced stackup RF material will create. ISOLA FR408HR offers decent performance. Ideally you would want to use a transceiver that has LiP (Launcher in Pad) which eliminate the need for on-board antenna array.

I've heard you say this many times with little explanation. Would love to see a dedicated video of why and what to do instead.