Every video is worth watching,but i wasted many hours watching other videos on this topic yet didn't understand properly...but understood v.clearly by watching ur video. Thanks❤
@thebeleiverrАй бұрын
Thanks mam
@prajaktamajalekar56883 ай бұрын
It's a bit of audio clarity problem your video is having... But this is the best explanation of octal to binary priority encoder... I was looking for this explanation only.... You're amazing...
@GauravGR143 ай бұрын
Very informative😊😊
@user-eu5kc5fs9p5 ай бұрын
ma'am master slave flip flops are edge triggered right?
@rohit.p71075 ай бұрын
Thank you maam you helped a lot for us tomorrow is our exam and iam watching your 2-3 videos they are so understandable now i can score good in exam 😃
@VarshiniVechalapu-fy8kk6 ай бұрын
Tq mam
@karthiksarode246 ай бұрын
pls do 4 sem alos
@Harsh-Yaaps6 ай бұрын
Tqsm it helped alot ❤
@bhavanakalluri33586 ай бұрын
thank you so much ma'am
@Jhansilakshmi9037 ай бұрын
MAM YOU CAN DO BETTER BUT THE LECTURE WAS GREAT LOVED IT😏
@sk.md.ashrafsir49188 ай бұрын
You explained very well mam
@tgbxing50610 ай бұрын
Wow 🎉
@rguktian243410 ай бұрын
mam, u seems to have more knowledge but not active in uploading to youtube ... waiting for your activeness
@casa142010 ай бұрын
Very good! Thanks!
@user-cr8jc1wd6q11 ай бұрын
Video is not clarity, sometimes it's blur
@MALLIKARJUNA_B_KUMBAR11 ай бұрын
Superb teaching mam
@kalarykousarkalarykousar171111 ай бұрын
Superb ossum explanation 🎉❤😊
@samrinnisha-rk7zi Жыл бұрын
Super 👏
@kingphoenixhiwatari Жыл бұрын
Thank you mam
@user-mv9wm2ip6h Жыл бұрын
Excellent 💯
@bhavyatanneru3571 Жыл бұрын
Nice explanation mam
@lalithmohan2558 Жыл бұрын
Mam ur lectures are soo good why have u stopped teaching... Plz upload continue teaching
@salemgamil Жыл бұрын
Dear Dr. Your explanation is excellence and more clear
@A1Tech6111 Жыл бұрын
Thanks medum
@sanvithshetty4234 Жыл бұрын
Mam electrical 21 scheme yotube channel madi
@mallikarjunpujari1905 Жыл бұрын
Mam JK latch JKFlipflop Videos are not there madam
@mallikarjunpujari1905 Жыл бұрын
Madam your explanation is excellence madam
@ameermuhammadroghani4617 Жыл бұрын
It is 74LS138? Or 74xx138 or both are equal?
@babymonsters16 Жыл бұрын
Both are same
@everythinggood42 Жыл бұрын
👌👌
@vidyashreen5002 Жыл бұрын
Very nicely explained all the logic connections, Now I am very much clear to explain to my students. I watched all your module 3 videos , textbook reading is not required after your explanation
@vidyashreen5002 Жыл бұрын
Hi Shilpa mam for D0 you can make one quad. Kindly check
@sanchiths677 Жыл бұрын
Love u mam super explanation
@meghabalikai1982 Жыл бұрын
Good teaching
@endrakantimanisha8050 Жыл бұрын
mam can you please upload videos on sequential circuits using cplds and fpgas...
@sygcreations2697 Жыл бұрын
thank you mam
@animalsworld9734 Жыл бұрын
Best
@rohitvinayakhegde4903 Жыл бұрын
mam could u make video on 18ec56, verilog hdl
@Madhu_BR Жыл бұрын
Spr
@kumarsanni5220 Жыл бұрын
Mam plzz help me to clear my supplies mdm
@twinthrottlers741 Жыл бұрын
thank u mam
@kaarthiksakthivel8284 Жыл бұрын
nice explanation appreciate it
@pratignasali6024 Жыл бұрын
There is no clarity on voice
@suprodippaul50432 жыл бұрын
Mam if SR latch is with Nor gate then the state of S=1&R=1 is Undefined But SR latch with nand gate then the state of S=1 & R=1 is Unchanged or previous data So when you connect the clock with latch for the flip flop then ur function table is some depends on the wich latch u connect. Here you add the latch of Nand gate but your state of last entry S=1&R=1 is will be Unchanged or previous data,right mam?but u saying that it will be Undefined . Please clear it mam can't understand I think there was a some mistake or casualty
@shilpav92452 жыл бұрын
SR latch with Nand gate function table remains same as S R latch with NOR gate . To clear your doubt now just give S=1R=1 to this circuit .,at the first level for upper NAND gate S=1,clk=1 so NAND gate output is 1,similerly for the lower NAND gateR=1, clk=1 so Lower NANad gate output also=1,Now these NAND gates iutputs are connected as input to the second level . Now at the second level to the upper and lower NAND gate one of the input is 0, if u recall NAND gate truthtable.,if any one of the input to the NAND gate is 0 then output is also 0 so both Q and Q' outputs are 0 ..as you know both the output cannot be 0 because Q' has to be the complement of Q so this output is called as undefined state of the flipflop.
@suprodippaul50432 жыл бұрын
Mam why you r doing Nand gate function table not according to sr latch with nand gate? U r doing SR flipflop with nand gate but ur function table is according to the SR nor and this is right mam?
@shilpav92452 жыл бұрын
Which topic u r talking about
@shilpav92452 жыл бұрын
This vedio is about master slave flipflop
@suprodippaul50432 жыл бұрын
(Requirement fullfill)no less ,no heavy discussion.only what we want to learn & have to learn
@priyankapatil75362 жыл бұрын
Ma'am are u teached any 4th sem subject from ENC dept ....?????plz reply me