(Requirement fullfill)no less ,no heavy discussion.only what we want to learn & have to learn
@gaganagt49763 жыл бұрын
Mam plz can u explain how to write that S R waveform
@ravinutalas25512 жыл бұрын
Thankyou madam....your explanation is very clear...understandable
@vatturivenkatapadmavathi13873 жыл бұрын
Well explained, mam
@sahanakumar883 жыл бұрын
vey much needed explanation of each topics, very helpful ...maa'm try covering all the topics by the time of examination .
@ramyaravindra35243 жыл бұрын
Ma'am it was very helpful thankyou somch
@harshahari37143 жыл бұрын
I'll thank you from my heart
@PreetiYadav-ng1kw2 жыл бұрын
Thanks
@chethanramachari54332 жыл бұрын
👍okay
@user-eu5kc5fs9p5 ай бұрын
ma'am master slave flip flops are edge triggered right?
@amitbohra62353 жыл бұрын
T flipflop is wrong, it is not extension to SR flipflop, it is extension to JK flipflop....rest all your videos are fine, kindly create a playlist though which would be easy to watch, and also include any videos left in between. Rest this is one of the best tutorial I have ever seen.
@Rameshram-ge7no3 жыл бұрын
Mam, Pls could you make video on DSD lab exam viva quetions pls ? I think how ever they will ask but atleast most expected quetions mam, pls make a simple video on that mam, we have lab exam on 16th of this month mam, 2 days remaining
@vengadeshr13693 жыл бұрын
Mam is there any videos for set up and hold time at flip flip in channel..?if not pls upload that.....
@umeshagoudapatil16593 жыл бұрын
Super explained mam which College mam
@suprodippaul50432 жыл бұрын
Mam if SR latch is with Nor gate then the state of S=1&R=1 is Undefined But SR latch with nand gate then the state of S=1 & R=1 is Unchanged or previous data So when you connect the clock with latch for the flip flop then ur function table is some depends on the wich latch u connect. Here you add the latch of Nand gate but your state of last entry S=1&R=1 is will be Unchanged or previous data,right mam?but u saying that it will be Undefined . Please clear it mam can't understand I think there was a some mistake or casualty
@shilpav92452 жыл бұрын
SR latch with Nand gate function table remains same as S R latch with NOR gate . To clear your doubt now just give S=1R=1 to this circuit .,at the first level for upper NAND gate S=1,clk=1 so NAND gate output is 1,similerly for the lower NAND gateR=1, clk=1 so Lower NANad gate output also=1,Now these NAND gates iutputs are connected as input to the second level . Now at the second level to the upper and lower NAND gate one of the input is 0, if u recall NAND gate truthtable.,if any one of the input to the NAND gate is 0 then output is also 0 so both Q and Q' outputs are 0 ..as you know both the output cannot be 0 because Q' has to be the complement of Q so this output is called as undefined state of the flipflop.
@Thegreatupscexam2 жыл бұрын
Mam can you upload network theory 3rd sem subject videos
@naveencherry57672 жыл бұрын
Mam can you please make one video for truth table of flipflops