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Пікірлер
@titiblob5126 13 күн бұрын
c’est un plaisir d’apprendre le VHDL avec vous ! Merci de partager ainsi vos compétences.
@cube1us Ай бұрын
Indeed. In watching your free VHDL episodes I winced every time you used the word "code". I prefer to use the word "logic". To me the point is that developing logic requires a different mindset that traditional programming/coding, because of the parallelism. For experienced people, it doesn't matter much, but using programming terms to describe logic in HDLs is, as the EEVBLOG host puts it, a "trap for new players".
@VHDLwhiz Ай бұрын
OK! I used the term "code" to avoid calling it programming. 😅
@LuigiCacciapuoti99 Ай бұрын
Why CountUp=CountDown at 40 ns? It should be at 50 ns
@VHDLwhiz Ай бұрын
No, because the signals change at 0 ns. CountUp goes from 0 -> 1 at 0 ns, 1 -> 2 at 10 ns, 2 -> 3 at 20 ns 3 -> 4 at 30 ns, 4 -> 5 at 40 ns. The signal assignments become effective when the "program" hits the Wait statement, not after the wait statement has completed (10 ns later).
@LuigiCacciapuoti99 Ай бұрын
@ thank you so much
@HJahm Ай бұрын
The Problem with me " Error loading design" what is wrong 😢
@VHDLwhiz Ай бұрын
Try to delete the compile library files with the command "vdel -lib work -all" and recompile. If that doesn't work, recreate the project. Possibly move the files to somewhere with a path containing no spaces or special characters. It's been a problem before but not with the latest versions of Questa.
@arsalansyed4709 2 ай бұрын
Thank you so much! You helped me a ton with my first internship
@rcherrycoke7322 2 ай бұрын
Is Vhdl Turing Complete ? If so it’s a programming language
@BillyMoloi-d8r 3 ай бұрын
Wow, very clear!
@EC-YOKESHS 3 ай бұрын
hi brother thanks for teaching this good one can you please explain about the CRC(cyclic redundancy check) that will be biggest help and also that chapter this in your youtube channel
@hojiafzal9559 3 ай бұрын
Hi Whiz, the traffic lights don't have to be part of the T20_TrafficLights.vhd entity, as the test bench is not using them. I moved them to architecture and remove them from the test bench entirely, and the system still works. I did this to prove to myself that I knew what (port) is about, which is to communicate with the outside world, in this case, the test bench. Thanks very much.
@priyaganesh4127 3 ай бұрын
Hi, This was working in my other system but now i got a new laptop and it is not working, getting this error: intelFPGA/19.1/modelsim_ase/bin/../linux/vish: symbol lookup error: /lib/i386-linux-gnu/libfontconfig.so.1: undefined symbol: FT_Done_MM_Var ** Fatal: Read failure in vlm process (0,0) Would be great if you can help me solving this issue.
@lowmax4431 3 ай бұрын
I imagine this is deceptively complex to implement in fpga fabric with no processor. I could be wrong though.
@VHDLwhiz 3 ай бұрын
Thanks. It's a bit challenging but doable. You have to approach the problem differently from how you would write a computer program. For the algorithmic part, we use a finite-state machine, and to store the game state, we use flip-flops (registers) and on-chip block RAM. But it's a lot easier when you have a good testbench (test simulation environment). In this case, we could play the game in the simulator GUI. I'm showing how to do that in the course mentioned in the video description.
@hojiafzal9559 3 ай бұрын
Dear Whiz, in T18_Timer.vhd, I added 'ticks' to the port and removed it from the architecture. Then in T18_TimerTb.vhd I added 'ticks' to the architecture and the port map. This worked. So my question is, what is the difference between your program and mine? What did I just do? In other words, in T18_Timer.vhd what is the difference between signals defined under entity and those under architecture? Thanks.
@VHDLwhiz 3 ай бұрын
The entity is just a way to pass signals between modules. If you defined the Ticks signal in the testbench and passed it to the module as an inout mode signal, there would be no functional difference. However, we can limit who can update signals by using "in" and "out" modes on entities instead of "inout" as we did in this example. Modes "in" and "out" are by far more common.
@hojiafzal9559 3 ай бұрын
@@VHDLwhiz Thanks a lot. As you can see, I am following all your lessons :)
@hojiafzal9559 3 ай бұрын
Hi Whiz, after I edit my file in Notepad++, modelsim does not update its local copy consistently. For a while it did ask me if I wanted to update the file, but that has stopped. How can I change this behaviour so after I save my changes in Notepad++, the modelsim version consistently reflects those changes, or at least ask me if I want to update the file? Thanks very much
@VHDLwhiz 3 ай бұрын
I usually close the editor in ModelSim and only use the external editor. Although, I've changed from Notepad++ to VSCode lately. Check out the "VHDLwhiz" extension for VSCode. I only use the Questa/ModelSim editor for debugging and placing breakpoints. I'm not sure if there's a way to make it reflect the changes faster. It's supposed to ask if you want to update the files you have open in the simulator editor. Sounds like there's something wrong. But, as I said, you don't really need the Questa editor except for placing breakpoints.
@hojiafzal9559 3 ай бұрын
@@VHDLwhiz Dear Whiz, I can't thank you enough for responding so promptly! I actually found a solution to my issue: from ModelSim INTEL FPGA STARTER EDITION 10.5b/Tools/Edit Preferences/By Name/Find you can search for "reload" and set "AutoReloadModifiedFiles" to 1. I wanted to update my inquiry here, but didn't think you would respond so quickly. Thank you so much!
@kenturkey1971 4 ай бұрын
Clarity on which is the local and which is the entity signal would have been nice.
@VHDLwhiz 4 ай бұрын
They behave identically. The only difference I can think of is that you can't write to "in" mode signals. If you want to distinguish them from local signals you can prefix their names with something, "in_" or "out_", for example.
@kenturkey1971 4 ай бұрын
@@VHDLwhiz I did a little experiment, where the mux is instantiated. The entity signal must be on the left, and the local must be on the right. That may be obvious to someone who's done it for a while, but I wasn't clear since all the variables are named the same. ("l_" is my local signal prefix in the Tb) This fails: i_Mux1 : entity work.mux(rtl) port map( l_Sel => Sel, l_Sig1 => Sig1, l_Sig2 => Sig2, l_Sig3 => Sig3, l_Sig4 => Sig4, l_Output => Output ); This succeeds: i_Mux1 : entity work.mux(rtl) port map( Sel => l_Sel, Sig1 => l_Sig1, Sig2 => l_Sig2, Sig3 => l_Sig3, Sig4 => l_Sig4, Output => l_Output ); Thanks for replying though!
@ChristianJacobsen 4 ай бұрын
For anyone using GHDL + gtkwave to do these tasks instead of ModelSim and are getting "error: integer overflow": Replace `integer` in the generic argument of the module with `positive`. That way we help ensure the compiler can prove we won't end up with a negative `DataWidth`.
@VHDLwhiz 4 ай бұрын
Thank you!
@theunknown5086 4 ай бұрын
Mann just found ur channel today and its a treasure❤
@OmarMohamed-ce9zv 4 ай бұрын
I followed all of the guide on Ubuntu 24.04 LTS and got this error in the end, can anyone help me in that : ./intelFPGA/19.1/modelsim_ase/bin/../linux/vish: symbol lookup error: ./intelFPGA/19.1/modelsim_ase/bin/../lib32/libfontconfig.so.1: undefined symbol: FT_Done_MM_Var
@gklinger 4 ай бұрын
Pointless semantics.
@aarondcmedia9585 4 ай бұрын
VHDL wizardry?
@PiezPiedPy 4 ай бұрын
Haha, good one.
@nikhilmaan9498 4 ай бұрын
jaat GPT ?
@Pratim-z7l 3 ай бұрын
Jaat pride 😤, VHDL Chaudhary 😊
@angelmba8797 5 ай бұрын
The state doesn’t change from NorthNext, I copied the code from the blog post
@VHDLwhiz 5 ай бұрын
Perhaps you're not simulating for enough time. The default in Questa/ModelSim is 100 nanoseconds, but you need to simulate for 5 seconds for the state to change. Try typing "run 10 sec" in the console. By the way, there is a demo Questa/ModelSim project that you can download from the article. Look for the "Need the ModelSim/Questa project files?" form on this page: vhdlwhiz.com/finite-state-machine/
@angelmba8797 5 ай бұрын
@@VHDLwhiz Thank you so much for your reply. It works fine now. Thanks for the video it was very helpful
@AhmadAsmndr 5 ай бұрын
i am using it ans as you said man should understand what it is doing, because it make a lot of mistakes also the 4O model. But it is absolutely a time saver. I am trying to optimize SPI-Master module with it since 1 Week and no success till now!
@DivyaSree-410 5 ай бұрын
sir iam not getting to open output window in modelsim .i have draged window but it is not displaying the output what should do
@huypixeltft6068 5 ай бұрын
why the vhld code is so small, how to zoom it in
@VHDLwhiz 5 ай бұрын
You can change the font size preferences in Questa/ModelSim Tools - Edit Preferences
@huypixeltft6068 5 ай бұрын
Help me with this sed: can't read ~/intelFPGA/19.1/model_ase/vco
@rickquackstley 5 ай бұрын
Thank you for this course! It is highly appreciated!
@diegogarridomendoza2828 5 ай бұрын
Hi Johan. Can I use Vivado and its TCL console to drive this testbench?
@VHDLwhiz 5 ай бұрын
You can do the same with Vivado but the Tcl commands will be different. It's one of the drawbacks compared to VHDL testbenches. Different tools have different commands.
@platinumpiglet5220 5 ай бұрын
great explanation! Thank you so much
@mwafakaljabi9611 6 ай бұрын
Thrilled for your course, dummy Q but; Did you use the Rpi, for the wireless connectivity? Isn’t it an overkill? Thank you
@VHDLwhiz 6 ай бұрын
It's the simplest solution I can think of. An Arduino may be cheaper but less flexible since it doesn't have Linux. Another way is to run Linux on a soft or hard-core CPU on an FPGA and let it do the work. FPGAs aren't suitable for implementing a network stack. It's possible, but it's much easier with software in my opinion.
@mwafakaljabi9611 6 ай бұрын
@@VHDLwhiz thank you for the quick response. As a junior electronics engineer with some PCB experience, are your courses useful for hardware developers too? Or usually hardware developers don’t develop in HDL code? Thank you 🙏🙏
@VHDLwhiz 6 ай бұрын
If I have to guess I would say that the company will probably not let you do FPGA design if they hired you as a PCB designer/electronics engineer. But I have seen people who did both at the same company. So not impossible.
@wojtess8613 6 ай бұрын
what protocol do you use to communicate with fpga? is this usb or uart?
@VHDLwhiz 6 ай бұрын
I'm using UART. The interface was created with my UART to FPGA register generator program: vhdlwhiz.com/product/vhdl-registers-uart-test-interface-generator/
@ryledesirabelli4151 6 ай бұрын
how do you declare std_logic in the entity ?
@gordonfreeman1894 6 ай бұрын
What board is it?
@VHDLwhiz 6 ай бұрын
This is the Lattice iCEstick
@msaufy 6 ай бұрын
cool!
@ahmedadam7202 6 ай бұрын
Wish had started watching your videos a while ago. I could have saved a lot of time.
@MRSBK-2002 6 ай бұрын
I am getting error while loading shared libraries: libXext.so.6:wrong elf elfclass64
@kfirmaymon84 6 ай бұрын
Wow this is amazing, Thank you so much for this.
@Jere393 7 ай бұрын
How can i alter the code that works In order activate (0,0), (0,1)... (0,7), (1,0).....(7,7)..
@ssBhaskar 7 ай бұрын
How to change font size of text editor
@dorshreal0016 7 ай бұрын
nice
@edadan 7 ай бұрын
I've been a Verilog coder since the early 90's and I'm new to VHDL...but, this just blew me away! Very elegant and efficient, but will take some time and practice to get used to this style.
@oussamaaziz4955 8 ай бұрын
Thanks.
@DAURYENTUBE 8 ай бұрын
please help me
@DAURYENTUBE 8 ай бұрын
Recommended procedure for performing laboratory work 1.develop a mathematical algorithm for solving the problem. 2.determine the required data types in the package. 3.study of differences in the design of functions and procedures in the VHDL language. 4.write the texts of functions and procedures. 5.write a test program. 6.Modeling and obtaining timelines. It is necessary to carry out testing of two functions and two procedures. task1. function (procedure) of double representation of the population presentation. This is a function (procedure) of the bit_vector type → INTEGER. Late (true) the rank of dual representation is assigned to the senior. The number of bits of the vector is equal to 8. task2. function (procedure) of preobrasovation of the first part of the presentation of the second part presentation. This is a function (procedure) of the integer type → BIT_VECTOR. First the rank of dual representation is assigned to the senior. The number of bits of the vector is equal to 8.
@manuelbojorge5840 8 ай бұрын
Sorry, but, how can I run it from quartus? Hehe I did it on windows but on Ubuntu nothing works
@serdarkalay6244 8 ай бұрын
ı could not understan why did you multiply with 10^6 inside the function
@ChiragHadiya 8 ай бұрын
hi, how can we also add the timing frame /scale of clock/ time showing like 1ps, 2ps, 3ps,..... above the clock signal ?
@ZaidEngComp 8 ай бұрын
you didnt declare which FPGA board name used ?
@adebayostephen7576 8 ай бұрын
I think it is Artix 7 35T Arty FPGA Evaluation Kit.
@amirayoob3706 8 ай бұрын
hello what is site name ?
@RJ-xe2dw 8 ай бұрын
# vcom -work work -2002 -stats=none C:/Users/rotho/OneDrive/Desktop/T01_HelloWorldTb.vhdl # ** Warning: (vcom-14) Failed to open "C:/Users/rotho/OneDrive/Documents/SUBJECTS/DigitalLogic/VHDL counter.mpf" specified by the MODELSIM environment variable. # No such file or directory. (errno = ENOENT) # Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 # ** Error: (vcom-66) Execution of vlib.exe failed. Please check the error log for more details. # # # Project file C:/Users/rotho/OneDrive/Documents/SUBJECTS/DigitalLogic/VHDL counter.mpf is write protected, data cannot be saved. # Unable to save project. 4:34 Please help
@still_alive02 9 ай бұрын
Vhdl is harder then assembly if i was a reverse engineer but want to design circuits with programming languages for now, how much time needs to switch? Tried qucs and multisim, seems like i don't know basics physics that needs for this
@VHDLwhiz 9 ай бұрын
You should install a free version of the Questa VHDL simulator: vhdlwhiz.com/free-vhdl-simulator-alternatives/ After you've done that you can go through my free beginner's VHDL course to learn the basics : vhdlwhiz.com/basic-vhdl-tutorials/