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Пікірлер
@112_tamilarasan_ece-a2 14 сағат бұрын
why you are use multiplier why not use finger .if we are use fingeer what will happen sir?
@kpj4985 3 күн бұрын
sir where is 2nd part or is this enough for BGR..?
@mvenkatesh5510 4 күн бұрын
I downloaded but i am unable instal windows 10 please guide me instal the tool ...it will really helpful to me ...
@analoglayout 4 күн бұрын
This pdk will support only linux environment
@_LeTanHuy-ky3jh 8 күн бұрын
The gpdk045_v_5_0 file must be in the root directory
@analoglayout 8 күн бұрын
Not mandatory, Non root user also can keep the data in their directory
@harshavardhann5292 13 күн бұрын
How to download 180nm bro
@analoglayout 13 күн бұрын
drive.google.com/file/d/1B3zDkcodAHz952q5sWFqKGzBZUSPmsQx/view?usp=drivesdk
@harshavardhann5292 13 күн бұрын
@analoglayout from this on cadence can I do gpdk 180nm analog,digital and layout design
@suresh.kannan 12 күн бұрын
Not possible @@harshavardhann5292
@sigityuwono9902 13 күн бұрын
watched 23.01.25. Thanks
@sigityuwono9902 13 күн бұрын
watched 23.1.25. Thanks
@sigityuwono9902 13 күн бұрын
watched 23.1 25. Thanks
@analoglayout 12 күн бұрын
Pls give me some valid comments
@sigityuwono9902 14 күн бұрын
watched 22.01.2025. Thanks
@sigityuwono9902 14 күн бұрын
watched 22.01.25. Thanks
@sigityuwono9902 14 күн бұрын
Watched 22.01.25. Thank you
@tolulopeagboola640 15 күн бұрын
You didntshow how it should be connected though in the layout, you were just talking
@analoglayout 15 күн бұрын
Better you can create video & share it on your own youtube channel, it's easy to give nagative command for other's work, better read my disclaimer content - as per my knowledge i created this video.
@nikithaathinamoni7026 15 күн бұрын
Hi how can we download ptm libraries to 45nm . Can you provide any link please
@analoglayout 13 күн бұрын
drive.google.com/file/d/1jMIAliVijAM0x_6Aqi98a0DuXlqlpERK/view?usp=drivesdk
@najmiaz-zahraferyputri653 17 күн бұрын
Thanks, but you should show how to add the ptab and ntab. It's funny how the video named is something like "prevent latch up" but all you do 80% is talk about what is latch up and 20% is how to prevent latchup. I need information about how to add the ptab and ntab.
@jeeveshvanga2598 17 күн бұрын
Thank you sir
@analoglayout 13 күн бұрын
Welcome
@Nobody_114 24 күн бұрын
Amazing!
@Nobody_114 24 күн бұрын
M0 OD is your contact layer for Source and Drain on the Fin. For the Poly Gate you need M0 PO. On top of either of those (M0OD or M0PO), you need V0 to connect to M1.
@Nobody_114 24 күн бұрын
Isn't there an NPLUS layer for the NFET (NMOS FinFET)?
@Everydaykaen 25 күн бұрын
Nice for my interview next week 😅
@rakeshlanderi8146 27 күн бұрын
net name is wrong in the layout -in2 ,please update it
@analoglayout 27 күн бұрын
Now it's not possible to edit, thanks for bringing this my notice
@gopisureshchowdary Ай бұрын
HI,Very nice video,I am looking for ANALOG LAYOUT Training in lower nodes offline .Can you please let me know about further details like fees and lab access ,i want 4-5 months hands on internship.
@analoglayout Ай бұрын
Sorry, I'm not the right person to ask about internship opportunities.
@gopisureshchowdary 13 күн бұрын
Is there any Analog VLSI Design training centers in Chennai bro.
@suresh.kannan 13 күн бұрын
Sorry my friend, no idea@@gopisureshchowdary
@suresh.kannan 13 күн бұрын
@@gopisureshchowdarysorry my friend, i have no idea
@taraldc Ай бұрын
very nicely explain the IR And EM
@analoglayout Ай бұрын
Thanks for the appreciation!
@rakeshlanderi8146 Ай бұрын
gate length is 60 nm which is wrongly mentioned !
@analoglayout Ай бұрын
Thanks for the notice
@tulasi_reddy Ай бұрын
I have downloaded the gpdk 45nm but when I am installing it on my laptop using the cmd command prompt it is not working.....anyone can suggest it to me.....
@analoglayout Ай бұрын
You need to setup environmental variables in basic file
@aceypan4601 Ай бұрын
thanks for sharing！
@mirzaamaan6937 Ай бұрын
Sir in video series of DNW( direct layers ) you showed DNW is consist of 2 diode psub and dnw diode Here we just have dnw diode what about psub diode Is it not necessary to have Please reply
@jayakrishnachalamalasetti1868 Ай бұрын
Than why we have to use inter digitization?
@yogeshrathour6705 Ай бұрын
Translate this in English also
@arshadatif6583 2 ай бұрын
Your voice is not audible
@analoglayout 2 ай бұрын
May be you can check your connection, no complaints about audio as of now from any other user
@Ajey24 2 ай бұрын
can you please updoad or send the 180nm gpdk. Thank you
@xuanvan6423 2 ай бұрын
Hi, do you have any materials or books for layout beginners? can you share the layout materials with me? thank you very much.
@analoglayout 2 ай бұрын
drive.google.com/drive/folders/1-Aj_1n_SS-U8k29WHqhYUOKeFqe8va2m
@arthura1687 3 ай бұрын
Dear Sir, Thank you for your videos! Could you please create a short video about cascoded current mirrors layout and their matching? Especially when the top and bottom devices have different lengths. Thank you again.
@analoglayout 3 ай бұрын
Send me some examples circuit with parameters
@arthura1687 3 ай бұрын
@@analoglayout M1(W/L=4/1, m=2) and M2(W/L=4/0.18, m=2) are NMOS diode connected devices in the reference path of a current mirror. M3 and M4 are in the output path, have same aspect ratios and m=8, thus mirroring coefficient is 4. What's the best method for achieving highest matching quality? Which areas more sensitive for mismatch, and, shall we add dunny devices on the edges only? Many thanks for your attention to this matter.
@chetancherry3 3 ай бұрын
please sir , i want gpdk180, can any one tell how to install
@analoglayout 2 ай бұрын
You need not to install, just extract the pdk & edit cds.lib file to point pdk directory & open virtuoso in the pdk directory
@ChetanPatil-tg2tb 3 ай бұрын
suppose if there is a separate guard ring for pmos and nmos , and if we do metal connection which passes over the guard ring from pmos guard to nmos guard ring does the connection establishes
@analoglayout 3 ай бұрын
I dont get you point
@ChetanPatil-tg2tb 3 ай бұрын
There is one pmos and one nmos which are in series, both have separate guard ring, and if we do metal connection for the mosses , were metal passes on guard ring, in these case the connection will be established?
@AmmaNanna-c1m 3 ай бұрын
Sir where the charges on m1 layer goes
@analoglayout 2 ай бұрын
After the fabrication of metal, there is a process called de ionization, this process will remove all the charges present in the metal
@AmmaNanna-c1m 2 ай бұрын
@@analoglayout thank you sir
@pavankarthik6380 3 ай бұрын
You explained which method to consider very nicely, can u also share your inputs on the patterns that we can go with the matching..?
@analoglayout 3 ай бұрын
Ok, sure
@endlesshope4 3 ай бұрын
How to find assura technology library file
@analoglayout 3 ай бұрын
What do you mean by ? Tech file
@endlesshope4 3 ай бұрын
How to find assura technology library file
@vimakuma 4 ай бұрын
Please explain the schematic and layout of BGR
@gaurav21rock 4 ай бұрын
Sir, How can we get access to Tsmc 16ff PDK ?
@analoglayout 4 ай бұрын
You should contact tsmc, only if you're eligible they will provide pdk
@jhanutelugufacts4332 4 ай бұрын
Sir plz do a vedio on choosing best patterns in common centroid matching. Your explanation is Awesome.
@analoglayout 4 ай бұрын
There nothing called best pattern, everything based on design constraints we select pattern
@jhanutelugufacts4332 4 ай бұрын
Thank you sir
@sv5144 4 ай бұрын
Why source and drain Should be merged..?..in schematic where it is showing
@analoglayout 4 ай бұрын
Without merging also we can do, but this will create od etching issue, sti, area waste, etc
@AhmedGamal-c1v 4 ай бұрын
How can I have a 7nm PDK?
@analoglayout 4 ай бұрын
Approach tsmc or samsung and get it
@sohamlakhote9822 4 ай бұрын
Thank you.
@analoglayout 4 ай бұрын
You're welcome!
@gundavishnu8039 4 ай бұрын
CPO-Cut Poly CMD- Cut MD Layer
@hamzaatiq203 5 ай бұрын
can we simulate this effect?
@analoglayout 5 ай бұрын
Yes you can
@harripoter7868 5 ай бұрын
Hi Sir , I am facing exactly same issue while performing LVS on 12nm tsmc finfet design , but i dont know whats the name of layer to add, can you help me in this regard ?
@analoglayout 5 ай бұрын
All the tsmc foundry have same name, psub2 layer, but before adding this layer consult with your senior person
@mahi888ab 5 ай бұрын
Please share more on finfet contents. Also, Can you share some resources where I can learn more about these.
@analoglayout 5 ай бұрын
Lower node video will create legal problem in tsmc, so couldn't upload
@mahi888ab 5 ай бұрын
👏👏very useful content.
@vermatushant 5 ай бұрын
cds617 is not working for me
@analoglayout 5 ай бұрын
You can better contact cad eda team if Any cad related issues, i cant help it on this