Introducing Vitis Tutorials
0:39
3 жыл бұрын
Vitis Platform Methodology
40:50
3 жыл бұрын
Version Control with the Vitis IDE
7:30
Пікірлер
@Legendary_reacher
@Legendary_reacher 5 күн бұрын
How can i program the device using .pdi file without jtag connections? can i use ssh to copy and then what should i do?
@ShubhanshuArya
@ShubhanshuArya Ай бұрын
hey tony how can i install apt on petalinux after booting the xillinx board
@alkaline3mc
@alkaline3mc 2 ай бұрын
Is this example still viable in 2024?
@lambaseded4845
@lambaseded4845 4 ай бұрын
This was hugely informative, thank you for making it available.
@Eckmuhl29
@Eckmuhl29 8 ай бұрын
I'm totally new about Petalinux, I always see people running it in a VM. Why not directly with a Linux machine?
@user-liao3450
@user-liao3450 Жыл бұрын
Here is the PDF file www.xilinx.com/content/dam/xilinx/publications/presentations/c_04_rtl_kernel_Vitis_Tutorial_webinar.pdf
@Bangbabes-kg1mo
@Bangbabes-kg1mo Жыл бұрын
Painful! Going off on tangents at every opportunity, a nearly nonlinear explanation of events. Listening to you felt like dragging my bare toe nail across tarmac
@AndySomogyi
@AndySomogyi Жыл бұрын
without narration, this is next to useless. That 'music' is SOOO annoying. Come on AMD, with all your resources, you can't even bother to narrate a video.
@imranhussain-yq2of
@imranhussain-yq2of Жыл бұрын
Can i install OS in zedboard/PYNQ Z2 Board
@jaimeruiz7966
@jaimeruiz7966 Жыл бұрын
Im stuck at step 2 of the tutorial (hardware link) with this error: ERROR: [CFGEN 83-2284] --sc tag applied to nonexistant port mm2s_1.s I wonder where is the part #2 of this tutorial, no update since 2021(?) hahahhahah
@albertshown3174
@albertshown3174 Жыл бұрын
WHERE ARE THE INSTALLATION INSTRUCTIONS? WHY ARE YOU USING AN ALREADY-INSTALLED MACHINE?
@Bangbabes-kg1mo
@Bangbabes-kg1mo Жыл бұрын
I know right, technical and detailed as the vid is... somewhat painful to extrapolate the information eluded to be within
@dimitriosmerkouriadis8375
@dimitriosmerkouriadis8375 Жыл бұрын
can i add axi4 stream interface to the new custom platform?
@306kern5
@306kern5 Жыл бұрын
Great Video, where can I get the spreadsheet you used?
@dimitriosmerkouriadis8375
@dimitriosmerkouriadis8375 Жыл бұрын
same code in vitis hls 2023 has stalls in cosim after max_burst_length_writes. i mean it writes 512 bits each cycle for 16 cycles then it stalls for 2 cycles and then same pattern, how can i fix it
@Bwajster
@Bwajster Жыл бұрын
Is the Vitis Vision library supported on a Windows OS ?
@michaelbonnet590
@michaelbonnet590 Жыл бұрын
Could we get a similar kind of guide on using bootgen, both CLI and GUI?
@mcbuddy2159
@mcbuddy2159 Жыл бұрын
@Ricky Su Can you answer @Shane Murphy - this is also interesting for me.
@mathiasdadisman9393
@mathiasdadisman9393 2 жыл бұрын
You are doing a great job on your channel!! I am suprised that you haven't researched P R O M O S M!
@kipropcollins4220
@kipropcollins4220 2 жыл бұрын
does it bother you that at this age we still have to go through steps like these to get some obscure platform working? come on, someone gotta be smarter than this
@guangxuehan8575
@guangxuehan8575 2 жыл бұрын
how to download
@fw3mbedded598
@fw3mbedded598 2 жыл бұрын
thanks a lot for such detailed instructions .. only by following this i was able to build and boot linux on my zcu104 board
@Kadir85Akin
@Kadir85Akin 2 жыл бұрын
I didn't understand how to make it with github. This solution generates local git repository folder. And then? How can I make a connection between the git folder with the github? All the video is not useful without this information.
@Bwajster
@Bwajster 2 жыл бұрын
How do I migrate the HLS Video Library onto the Vitis Vison Library?
@Bwajster
@Bwajster 2 жыл бұрын
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
@Bwajster
@Bwajster 2 жыл бұрын
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
@Bwajster
@Bwajster 2 жыл бұрын
Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?
@bhagathch7349
@bhagathch7349 2 жыл бұрын
Hi, Is there a tutorial to use the generated IP from Vitis HLS and use it in a Vivado project?
@chillydickie
@chillydickie 2 жыл бұрын
do you code with the piano keyboard? haha
@miklosbence3852
@miklosbence3852 2 жыл бұрын
Hi, I have all restpect for the person holding this presentation for his knowledge and intention to help, still, his English pronunciation is terrible. It was not a good idea to ask him to talk in this video. For God's sake, asking a native speaker for a narration task has nothing to do with racism or thinking bad of Asian people. Please be rational. Thank you.
@deathmaster4035
@deathmaster4035 Жыл бұрын
Turn on the closed captions.
@andreabonatti5018
@andreabonatti5018 2 жыл бұрын
Tony you have officially become one of the deities in my little temple of all the people on the internet that helped me with a university project. The Xilinx guide was helpful but with someone explaining its contents it becomes much easier. Again thank you.
@SBUCompEngr
@SBUCompEngr 2 жыл бұрын
Thanks for the vid! Do you have a Vitis Debug tutorial with FSBL?
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 2 жыл бұрын
Please refer to this article xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842019/Zynq+UltraScale+FSBL?f=print#ZynqUltraScale%2BFSBL-I%E2%80%99munabletodebugFSBLinVitis.AnychangeinoptimizationsusedbyFSBL%3F
@robv3872
@robv3872 2 жыл бұрын
Thanks for making this! Hope to see many more!
@sleeplessdev7204
@sleeplessdev7204 2 жыл бұрын
I think I'm at the precipice of understanding, but I'm hoping you can clarify something for me. I have a decent understanding of how computers work at the level of transistors forming logics gates, and logic gates being combined into more complex structures like latches, flip-flops, and registers, but things get a bit fuzzy for me at higher levels of abstraction. So whenever I imagined the engineers at CPU manufacturers designing a new CPU, I pictured engineers actually placing registers, buses, and ALUs into a circuit and all the wires in between them into some design software, which then gets printed out onto a silicon die. This struck me as crazily complex given the scale of modern CPUs in comparison to individual registers. However, after hearing about High-Level Synthesis in a podcast, I was made to realize a different possibility that seems much more feasible: that perhaps those engineers actually just write C code, and use tools like this to generate circuits that are optimized for it. Is my new understanding about how this process works accurate, or am I still missing something? I'm really interested in learning how CPUs are designed and created. Thanks.
@fernandoi8958
@fernandoi8958 2 жыл бұрын
I am also new to this, but I don't think cpu manufacturers use hls. It looks like this is more suited to coding user applications that need hardware acceleration without the need to look into the details of the hdl code. Computer manufacturers definitly do what you said about placing specific components and linking them, but I think it is more of in a block diagram way for well-known stuff and hdl code for more specific blocks.
@lowmax4431
@lowmax4431 Жыл бұрын
ASICS are often created by writing HDL (verilog or VHDL) which is NOT high level synthesis. High level synthesis is geared towards people that are more comfortable with C/C++ but want to accelerate certain algorithms with FPGA hardware.
@catonyx
@catonyx 2 жыл бұрын
It would be helpful if it there was instructions on how to separate the workspace from the working directory. Or even if something explained which files should be kept under versions control versus those that are generated. After some experiments with Vitis IDE 2021.1, it seems that these are so intertwined, that I must just submit nearly the whole workspace to version control. This is bad since it includes stuff that is developer specific (like the eclipse layout). I only blame Xilinx for this confusion (not the presenters fault). This should be easy but it never is. And the tools should not force developers to use git -- it should be easy to use any version control tools.
@shanemurphy3403
@shanemurphy3403 3 жыл бұрын
But this will commit the .prj and .sprj files which contain absolute paths, breaking the build on any system but your own. How do you share the project then?
@RachelGaines-yh9ly
@RachelGaines-yh9ly 10 ай бұрын
Hi @shanemurphy3403, you need to open the project.spr BEFORE you build the platform. The path will update to the imported project path so that the platform project will build correctly. You can verify the change in the log files after it builds.
@MukeshGhosh123
@MukeshGhosh123 3 жыл бұрын
Hello Adaptive Computing Developer, After doing this same video simulation, I am getting error something like .elf does not exist "[Common 17-275] File does not exist [c:/Users/Mukesh Ghosh/Versal_NoC_practice/Versal_NoC_practice.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_7/ip_0/bd_8be5_MC0_ddrc_0_phy_ddrmc.elf]" How can I solve this error and do you have any idea why I am getting this error.
@ronsalesky4428
@ronsalesky4428 3 жыл бұрын
Thank you for an excellent and comprehensive introduction to the Petalinux build process. Regarding using Petalinux sstate cache artifacts, how does one deal with a situation such as for version 2021.1 where there is both sstate and downloads available plus sstate-update1 and downloads-update1. How are they specified in the petalinux build process?
@novavela
@novavela Жыл бұрын
Did you find the answer to how to manage the updates and downloads packages ? Are they cumulative updates ?
@gocomputing8529
@gocomputing8529 3 жыл бұрын
Can you configure the clocks as it is done in Zynq platform instead of the way shown here?
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
At 1:05 this tutorial configured the input clock pin frequency. It's matching the real hardware. This tutorial didn't configure clock output in CIPS or clock_wizard. You can configure these output clock signals. The configuration method is similar to the ZYNQ platforms.
@TheAstronomyDude
@TheAstronomyDude 3 жыл бұрын
Can it run regular Linux, like a Raspberry Pi ?
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
Please check out Ubuntu on Xilinx boards ubuntu.com/download/xilinx
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
From Tony: The PetaLinux tools build a custom Linux operating system using firmware, Linux kernel, and packages. PetaLinux itself doesn’t run anything. But, Xilinx has partnered with Canonical to create a Certified Ubuntu for Xilinx Devices release. You can download it from the official Ubuntu site here: ubuntu.com/download/xilinx. We have information about using it on the Xilinx wiki here: xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2037317633/Getting+Started+with+Certified+Ubuntu+20.04+LTS+for+Xilinx+Devices
@Ali-wf9ef
@Ali-wf9ef 3 жыл бұрын
why is the vector size set to 64? Shouldn't it be 16? 16 unsigned integers to match the one without vector data type.
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
From Frederic: The GCC "vector_size" is in bytes... Therefore 16 integers (32-bit) is 64 bytes... Note that HLS provides a library hls_vector.h that makes it easier to specify these vectors: docs.xilinx.com/r/en-US/ug1399-vitis-hls/Vector-Data-Types
@laylash2531
@laylash2531 3 жыл бұрын
Please I want frame buffer code in c++.please help me
@tahirsengine
@tahirsengine 3 жыл бұрын
Hey Tony, it was great to see this video. It will be great if you upload a project that takes things from VHDL, block diagrams to Petalinux. Define different parts and how can we configure them. Maybe a small series of lectures will be great. Especially when we want to store system contents on QSPI and eMMC. Actually, I am an HDL FPGA /ASIC guy and I am really looking for some sources that can teach me FPGA software design flow. Your lecture was anyway great. :)
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
From Tony: Thanks for the kind words. This is really good feedback and a really good idea for future content. This video was intended to be an overview of the PetaLinux process without too much depth but there are definitely things that can be covered in more detail.
@myetis1990
@myetis1990 3 жыл бұрын
should have focused on the filesystem packages explanation.
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
From Tony: Thanks for the feedback. I agree that there’s a lot more detail about the package groups that I _could_ have gone into but then the video would have been much longer. The goal of this video was to give an overview of the general process. If you’d like to see content about the package groups themselves, I’ll consider it for a future video.
@henryhowland3686
@henryhowland3686 3 жыл бұрын
This is great, thanks
@tolgacar
@tolgacar 3 жыл бұрын
Hello, ı would ask question.. Is Vivado HLS and Vitis HLS same application? If not, whats differences? Thank you.
@cheikhsakka8185
@cheikhsakka8185 3 жыл бұрын
Hi did you find answer? by the way I would appreciate help from you, i am a beginner, a real one !
@Me-ty8ey
@Me-ty8ey 3 жыл бұрын
hai please may i know did you get the answer?
@cheikhsakka8185
@cheikhsakka8185 3 жыл бұрын
@@Me-ty8ey are you working on viitis ?
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
Vitis HLS is the latest Xilinx high-level synthesis tool. Please checkout the Vitis HLS migration guide for more details. docs.xilinx.com/r/en-US/ug1399-vitis-hls/Migrating-to-Vitis-HLS
@mathewbenson5447
@mathewbenson5447 3 жыл бұрын
Did I hear the intro correctly? “Version control is NOT commonly used in development?”
@sutongqi
@sutongqi 3 жыл бұрын
Version control is NOW commonly used :)
@Kadir85Akin
@Kadir85Akin 2 жыл бұрын
I also hear 'not', but the subtitle makes it clear.
@CornelisVermazen
@CornelisVermazen 3 жыл бұрын
Thanks for the good explanation (Perfect).
@franciscofer9443
@franciscofer9443 3 жыл бұрын
Hello! Can I modify the RTL code generated by vivado HLS later on in my Vivado project?
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
Yes, you can, but it's often better to think about the generated RTL as a kind of intermediate product. if you rebuild your code in HLS, for instance, the generated RTL would be rebuilt as well and your changes would need to be re-merged.
@keyvanshahin1740
@keyvanshahin1740 2 жыл бұрын
@@adaptivecomputingdeveloper4413 thanks for the response. but still working with and modifying the RTL is possible right? I read somewhere that the RTL is not insured to work and you can only rely on the generated IP. Can you elaborate please?
@basharromanous4703
@basharromanous4703 3 жыл бұрын
Thank you so much!
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
You're welcome, hope it helped!
@FPGASystems
@FPGASystems 3 жыл бұрын
Finally Xilinx at the end of his life started a series of educational videos. Better late than never. Thanks for materials, subscribed.
@adaptivecomputingdeveloper4413
@adaptivecomputingdeveloper4413 3 жыл бұрын
Thanks, more to come!
@ZatoichiRCS
@ZatoichiRCS 4 ай бұрын
After they came after those trying to teach FPGA technology and the prices in the US are outrageous while they are peanuts in rival nations. They are not doing us any favors. This company and Intel are just as bad for National Security.