Introduction to Vitis High-Level Synthesis (HLS)

[@bhagathch7349]

Hi, Is there a tutorial to use the generated IP from Vitis HLS and use it in a Vivado project?

[@franciscofer9443]

Hello! Can I modify the RTL code generated by vivado HLS later on in my Vivado project?

[@adaptivecomputingdeveloper4413]

Yes, you can, but it's often better to think about the generated RTL as a kind of intermediate product. if you rebuild your code in HLS, for instance, the generated RTL would be rebuilt as well and your changes would need to be re-merged.

[@keyvanshahin1740]

@@adaptivecomputingdeveloper4413 thanks for the response. but still working with and modifying the RTL is possible right? I read somewhere that the RTL is not insured to work and you can only rely on the generated IP. Can you elaborate please?

[@Bwajster]

How do I migrate the HLS Video Library onto the Vitis Vison Library?

[@Bwajster]

Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?

[@sleeplessdev7204]

I think I'm at the precipice of understanding, but I'm hoping you can clarify something for me. I have a decent understanding of how computers work at the level of transistors forming logics gates, and logic gates being combined into more complex structures like latches, flip-flops, and registers, but things get a bit fuzzy for me at higher levels of abstraction. So whenever I imagined the engineers at CPU manufacturers designing a new CPU, I pictured engineers actually placing registers, buses, and ALUs into a circuit and all the wires in between them into some design software, which then gets printed out onto a silicon die. This struck me as crazily complex given the scale of modern CPUs in comparison to individual registers. However, after hearing about High-Level Synthesis in a podcast, I was made to realize a different possibility that seems much more feasible: that perhaps those engineers actually just write C code, and use tools like this to generate circuits that are optimized for it. Is my new understanding about how this process works accurate, or am I still missing something? I'm really interested in learning how CPUs are designed and created. Thanks.

[@fernandoi8958]

I am also new to this, but I don't think cpu manufacturers use hls. It looks like this is more suited to coding user applications that need hardware acceleration without the need to look into the details of the hdl code. Computer manufacturers definitly do what you said about placing specific components and linking them, but I think it is more of in a block diagram way for well-known stuff and hdl code for more specific blocks.

[@lowmax4431]

ASICS are often created by writing HDL (verilog or VHDL) which is NOT high level synthesis. High level synthesis is geared towards people that are more comfortable with C/C++ but want to accelerate certain algorithms with FPGA hardware.

[@laylash2531]

Please I want frame buffer code in c++.please help me

[@tolgacar]

Hello, ı would ask question.. Is Vivado HLS and Vitis HLS same application? If not, whats differences? Thank you.

[@cheikhsakka8185]

Hi did you find answer? by the way I would appreciate help from you, i am a beginner, a real one !

[@Me-ty8ey]

hai please may i know did you get the answer?

[@cheikhsakka8185]

@@Me-ty8ey are you working on viitis ?

[@adaptivecomputingdeveloper4413]

Vitis HLS is the latest Xilinx high-level synthesis tool. Please checkout the Vitis HLS migration guide for more details. docs.xilinx.com/r/en-US/ug1399-vitis-hls/Migrating-to-Vitis-HLS