3 Bit Asynchronous Down Counter | Sequential Logic Circuit | Digital Circuit Design in EXTC

Explore the fascinating world of digital circuit design with this tutorial on the 3-bit asynchronous down counter. Delve into sequential logic circuits and master the principles behind this essential component. Discover how it functions, its role in digital systems, and its practical application in the realm of electronics and telecommunications (EXTC). Join us for an insightful journey into the heart of digital circuitry and enhance your understanding of sequential logic circuits through clear explanations and illustrative examples. Whether you're a student or an enthusiast, this tutorial is your gateway to mastering this fundamental aspect of circuit design.
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[@turaysamuelm.4445]

Words can't express how much i love your tutorials🙏❤️

[@anishrajak693]

The circuit diagram is incorrect Next clock pluse must be given from Q' for a negative edge trigger down counter

[@musarrat1050]

yes

[@ck-hq5iq]

or we shall use possitive egde for if we go with qn

[@neerala2424]

Nice Video 👍 mam I cannot understand anywhere 🥰 But your vdo is understood me .... Thanks 🙏 mam.

[@thepahadiclasher3926]

Our professor told us to use the complemented output as the clock for 2nd ff and 3rd ff...

[@PhaniManjunath.]

Thank u mam

[@Aashish0049]

As far as I know, the state changes on the positive in the downcounter. 🤔

[@Humordose_op]

Thats not right brother It changes on negative edge only

[@Molecularphysics12]

But If output Q is connected with negative edge triggering to clk pulse then its down counter

[@priyadarshiroy9584]

Up counter not down

[@yashSharma-fn8fm]

Bhaiyon ye circuit diagram galat bana he

[@Aashish0049]

State changes on +ve edge trigger or, on -ve edge trigger , in Downcounter

[@rabin2439]

You can change it on any state bro, either positive or negative.

[@VikcyAnthati]

Super akka

[@VikcyAnthati]

😘

[@muqadasakram6587]

Agr down counter k liye counts krna ho 15 to 0. And clearly show timing diagrams of all the states

[@RaviYadav-bj6mw]

diagram is wrong I think

[@yashSharma-fn8fm]

Bhaiyon ye circuit diagram galat bana he

[@queenieluong]

periodddt queen

[@yashSharma-fn8fm]

Bhaiyon ye circuit diagram galat bana he

[@muqadasakram6587]

Hello mam

[@muqadasakram6587]

Jaise ap ny yaha py 8 li thi waise he hum 15 ly gy

[@Simran_Kodere]

Wrong diagram

[@sanketkumbhar]

How

[@sanketkumbhar]

Can you explain me please 🤔

[@musarrat1050]

yes

[@shitalghodmare1274]

Because Qbar is given input as a clock

[@ramrajedeshmukh2783]

Yes