3. SR Latch using NAND Gates | Tech Gurukul by Dinesh Arya

[@knowledgegrooming8186]

Delhi should proud on such type of teacher. Welldone sir great

[@aakashsaini4789]

Thanks sir, I am student from govt. polytechnic jhajjar and i wanna say that you are doing great job. You explain concepts in very simple way so there is no space for the doubts❤

[@parthasauravroy8910]

Thankfulness and respect to you, sir, from Dhaka, Bangladesh.... This is the best class of Latch!! Take my pranam, sir.... 😍😍❤️❤️🙏🙏🙏

[@legendarygamers5370]

Lol

[@anshbairagi7620]

sir i cant tell you how helpfull and good your lectures are thank you for your efforts❤

[@swarnalisaha9770]

Thank you sir...it was so easy to understand.😇

[@nixuzumki5150]

far better than tutorial point totally understandable your lecture sir..

[@creativeworld2860]

bhot khoob sir bhot acha guide kia ha nice

[@engrafaqali6884]

Good sir best way meny sary videos dekhen mgr mjy smjh m nhn aa rha tha or apki video m sara smjh m aagya

[@TechGurukul]

thanks

[@engrafaqali6884]

@@TechGurukul sir please agar apki clocked sr latch ki video hy to us m comment m mjy mention kren.

[@andythomson2227]

Crystal clear teaching 0 to hero teaching sir

[@TechGurukul]

Thanks for your appreciation 🌹

[@TechGurukul]

Thanks for your appreciation 🌹

[@yaduvanshivlogs6470]

Sir your teaching method is very good I am happy because my concept easily clear only one time see

[@shivansh.speaks]

great lecture sir , thank you so much

[@prittambehera5291]

Very Very Thank you Sir for this video 👍🏻👍🏻👍🏻

[@VAISHNADEVIGECEUG-]

THANKYOU SIR I UNDERSTOOD THE CONCEPT CLEAR SIR

[@Tanveer048]

it was so easy to understand.😇

[@rohanpal7215]

Sir you explain very well ❤️🔥 OP 🔥

[@vinodkumaryadav1002]

Gjb theching quality sir

[@khananas4769]

Thank U so much sir ❤️ aap k samzane ka triqa bhut acha lga 👍👍👍

[@feelingtoday6340]

Sir your words are very clear and concise.

[@adityasrivastava8790]

Sir keep going..Gr8 work!!!!

[@TechGurukul]

Thanks

[@adityasrivastava8790]

@@TechGurukul Welcome sir..You all are heroes!Cheers..GGMU

[@PardeepSingh-wj8lc]

Queries hona toh impossible h😎

[@rahulraj-eg6ic]

Kya kuch samaj ni aya sir😂pr your way of teaching was❣️❣️

[@sushmanaik2228]

thank you sir, when set is high the output becomes one.. but why in nand latch output is considered as low when set is high??

[@tejaskakad4229]

When S = 0 and R = 0, the outputs can be either q = 0 and q' = 1 or q = 1 and q = 0, for all the three cases mentioned above. Is there a way you could explain the S = 0 and R = 0 case again? Thank you!

[@jaydevbhadreswara423]

Thank you so much sir🙏🏻💐 For best teaching

[@gautamnaugai.iab94]

Sir hamari collage me aap aajao padhane hamari mam bahut shortcut krke padhati hain wo sirf projector se samajati hain Sir aap bahut aache se topic smajha rahe ho😊

[@afjalsherasiya7904]

Thank you so much sir ❤️❤️

[@asifzamanrizve4435]

Thank you sir. These videos are truly helpful. Thank you sooo much.

[@sabaalam8031]

Sir ap ki video bhot helpful ha mashallah Allah pak ap ko is ka ajr dy! Is ki mujy bilkul smj nhi a rhi thi lakin ap ki video wounderful nice❤💘

[@ruchikashyap1999]

Thank u so much sir.. It's crystal clear 🙏

[@jyotirmoykalita3958]

😂

[@JustinZaf]

thank you so much and there is no need for the intro and end music

[@TechGurukul]

OK 💐

[@ichwanwiradarma8518]

Gerendel (latch) yg dibangun dg pintu NAND gate atw pintu NOR gate, inputnya langsung di oper ke output. Flip-flop RS seperti ini, operasinya tdk singkron dg denyut-2 lonceng atw denyut-2 penentu waktu (timing pulses), dalam operasi flip-flop RS seperti ini tdk diperlukan sinkronisasi dg operasi sirkit-2 lainnya...., krn itu diterapkan sbg ingatan..., itu saja dulu.....

[@shivramchoudhury]

Why do we interchange the SET and RESET inputs in NOR and NAND based S-R Latch???????

[@1ksubscribechallengewith605]

Same question??

[@shivinwestwood]

@@1ksubscribechallengewith605 Because the truth table of NOR and NAND are totally opposite.

[@sourakantimandal6026]

Awesome sir awesome !!! 👍👍👍👍

[@TechGurukul]

Thanks for your appreciation 🌹 💐

[@sourakantimandal6026]

@@TechGurukul Thanks for your time and reply Sir, Pranaam Lena 🙏🙏🙏

[@sawerasawi.7159]

Thanks sir hand writing nice

[@youtuberparmotiya1118]

Sandar sir G

[@hafizaanilasajid5733]

You are great Sir.

[@shivinwestwood]

4:39 why the output of Q' is feeded to the upper gate, As the upper state haven't completed first iteration.

[@sujitbeheramali6269]

Sab perfect he❤️

[@meenakhan1341]

thank u sir 😍

[@laibakhan6415]

its really helpful

[@fakhrabashir6471]

Thank you so much sir

[@sonam6493]

thank u too much sir 🙂🙂

[@ratanmanisingh9323]

Sir, in implement of SR filp flop using NOR gate we take input as R and S But in NAND gate we take always S and R Or we take it R and S also

[@TechGurukul]

To denote S- set and R-reset state

[@TechGurukul]

To denote S- set and R-reset state

[@ratanmanisingh9323]

Thank you, sir

[@Pgm123-y9b]

Thanks sir

[@borusutejeswari1538]

Sir but the truth table of Dr latch is totally different from sr flipflop in conditions of ,if s=1 then q=1 right bt here it's not ..?

[@TechGurukul]

Yes ckt is also different

[@borusutejeswari1538]

@@TechGurukul if we take next state for every combination of s&r in latches that is qn+1 state then wt it's output sir ..Is it give SR flipflop outputs

[@student4145]

Thank you Sir!!

[@siddharthsharma3810]

Sir ek questions h ki hm latch ko nor aaur nand gate se kyoi bnate h ?

[@aashutoshprajapati6362]

Thank you sir

[@Peterparker-v6h]

Sir,why we used not gate after s,r inputs and then we make r, s latch using nand gate❓❓❓❓

[@kalpanachintakula481]

Sir u have said that when s=0,Q=0,when coming to the circuit operation for s=0,the outputQ=1can u explain it once again

[@TheJokerandTheJean]

Sr latch with nor gate is active high and with nand gate it's active low....

[@m.umairsaeed1753]

Sir ap case mai S or R ky values kaha sa la rahay h

[@prafulnchikkamath1856]

What is the set and reset there?? If s== 1 Q should be 1 na? Set Similarly reset ???

[@رمشهجيلاني]

i have a question k jb humne case 3 me output bhi mita dia and new se kia sb to case 4 me output nahi erase kia?? means how do i know k kon se case me output ko feedback krna hai or konse me erase krna hai?? plz ans

[@hafizaanilasajid5733]

I have same question.

[@karnox.24]

sir apne last case 1,1 me mspne kyu S ya R ko kesi ek ko bhi qn me zero nahi rakha

[@rajnishraj9576]

final truth table mein set and reset kya hoga sir ?

[@vanrajsarvaiya5714]

Why undesirable s0 and r0 for nand and vise versa for nor

[@TechGurukul]

Because in that case both outputs will be high. And that state is not true because output should be compliment of each other.

[@vanrajsarvaiya5714]

@@TechGurukul but why it should be compliment

[@aakashgautam2200]

@@vanrajsarvaiya5714 did you found the answer ? please post if found.

[@JustinZaf]

Thanks btw so much h

[@prashantsharma7788]

❤️❤️❤️❤️❤️

[@residualbin]

Nor 1000 11 Nand 1110 00

[@alveenairum6994]

kindly timmig diagram bhi banain

[@aayeshakhan9914]

Sir aapne kaha set me Q= 1 aayega but truth table me Q ki value 0 kyu hai jab S=1 hai...please answer!

[@shivinwestwood]

S=1 (set) where Q= 1 it is In NOR latch, Here you are studying NAND latch.

[@amandeepthakur7847]

in previous video S corresponds to Q' but in this video S corresponds to Q???why?

[@Sachin-hc1nj]

Sir input interchange nahi Kiya toh ...is that.okay..?...(RS likha toh instead of SR input)

[@HM-sid]

Sir why we change the position of set and reset in nand ?

[@jojid.econar280]

That is the standard position of nand gate according from tutorialspoint

[@20shwetha]

Sir you told when set is 1 in q=1,but we are getting q=0

[@20shwetha]

Please reply

[@feelingtoday6340]

0' has been like capital 'D'😁😁

[@sheruloves9190]

Ty

[@jumanji3426]

sir u have done wrong for sr latch using nand gate. the truth table is wrong where u have s=0,r=1 q should be 0 and q'=1. please confirm this

[@diptiranjanmishra9979]

Sir can contact with you

[@talhakahloon7890]

if s=0 &r=0 and after it we put s=1&r=1 what is the q and q"

[@talhakahloon7890]

@@-EE-ShahbazHussain thanx

[@PardeepSingh-wj8lc]

Msttt

[@Q4Curiosity]

❤️

[@bibex69]

sir aap ki sr latch ki truth table wrong hai mere khyal se kyu ki 2nd case me reset condition hota hai jo ki 0 1 hota hai aap ne 1 0 kiya hua hai jo ki set condition hai or ye galt is trha se bhi hai kyu ki hum humesha S input ke samne Q bar rkhteh hai output par or R input ke samne Q agr aap aisa ni rkh ke jaisa video me hai waisa rkhna chahite hai to aap ko dono input ka compliment rkhna hoga ye sare rules nand gate ke sath lagu hote hai

[@TechGurukul]

No, this is right. is ckt. k according yahi truth table hogi. go through the video .

[@laibakhan6415]

incase of NAND gate S ke samny hamesha Q ayega or R ke samny Q' ayega and in NOR gate S k samny Q' or R k samny Q ayega.

[@nidhideshpande4292]

It's s bar and r bar.. But it's not here

[@ravikumarb9104]

👍

[@Jharkhand-c8u]

Sir meine panchayat sachiv exam clear Kiya hai Lekin form apply karte smay 12 compartmental pass ki jagah 2nd division likha hai.. documents verification mein mujhe kya problem hoga??? please reply

[@jkkushwaha3968]

Thank you, so much sir 🥰

[@jaydevbhadreswara423]

Thank you sir

[@btechmathsclasses3034]

Thanks sir