SR Latch and Gated SR Latch Explained | SR Latch using NOR gates and NAND gates

In this video, the design and working of the SR latch and the Gated SR latch are explained in detail. In the video, the design of the SR Latch using the NOR Gates and NAND Gates is explained, and how this Latch responds to the different input combinations of S and R is also explained in detail.
The following topics are covered during the video:
0:00 Design of Basic Memory Element using Logic Gates
3:30 SR Latch using NOR Gates (Logic Circuit, working and Truth Table)
11:18 SR Latch using NAND Gates (Logic Circuit, working and Truth Table)
16:18 Gated SR Latch
19:14 Gated SR Latch using NAND Gates
23:50 Gated SR Latch Timing Diagram
The link for the other useful videos:
1) Latch and Flip-Flop:
• Latch and Flip-Flop Ex...
2) Introduction to Sequential Circuits:
• Introduction to Sequen...
3) Digital Electronics (Playlist)
bit.ly/31gBwMa
SR Latch:
The SR latch has two inputs (SET and RESET) for setting and resetting the 1-bit of information.
And it has two complementary outputs Q and Q'.
When S is 1 and R is 0 then latch Sets the output to logic '1'.
When S is 0 and R is 1 then latch Resets the output to logic '0'.
And when both S and R inputs are 0 then latch retain the currently stored information.
In the active high SR latch, S = 1 and R = 1 input combination is forbidden.
In this video, the SR latch is designed using NOR gates and NAND gates. And the working of the latch is explained for the different input combinations.
Gated SR Latch:
The normal SR latch is transparent, because it immediately responds to the change in input .
But the Gated SR latch has control / enable input. When this enable input is high, then only it becomes transparent to the inputs. In this video, the design of Gated SR latch using the NOR gates and NAND gates is explained.
And its working is explained using the timing diagram.
This video will be helpful to all the students of science and engineering in understanding the Design and working of SR Latch and Gated SR Latch.
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[@shekharchaurasiya5236]

Very very thank you for this awesome lecture. Everything came naturally one after another.

[@christopheracob3689]

I appreciate hearing the word circuit now unlike others they were pronouncing as cirkyut...

[@ececse]

thankyou sir you made the concept crystal clear

[@josedominguez2021]

Exelente explicación. Muchas gracias!!!

[@poojashah6183]

Thank you sir for making it premier so that we can ask you anything as you are available here

[@mohammadrezajavadi3498]

Excellent explanation

[@bhanuprakashagrawal2921]

Great concept sir

[@uhuruplato5262]

Well explained.. And very clear.

[@shilpapatel793]

Great 👏👏👏👏👏

[@sarabuvenkatasarayuharika7604]

Excellent explanation sir 👌😌

[@mayurshah9131]

Please continue such informative and useful vedios,God bless you

[@ukeditz3]

thank you sir

[@churchilokech4778]

thank you so much

[@omerturnnn]

Thanks for sharing with us. Can you tell me which software did you use for drawing timing graphics?

[@itslegit07]

❤️❤️❤️

[@KapilKumar-xz9ip]

In the last example of gated SR latch with clock here sir use SR latch having NOR Gate and S corresponds to Q' & R corresponds to Q . that's why it is confusing sir, not mentioned it. Now what it again you can understand.

[@janu385]

Sir, gated sr latch timing and level triggered flip flop. Are both same or is there any difference

[@thisissaroj941]

well explained...keep continue to upload so more videos i will support you dear😊

[@saddamalgafsi6721]

3:55 the output should be low instead of high, otherwise very good explanation, keep it up! 😁

[@nihar8783]

can you please provide slides

[@6blak197]

3:04 explain about this 2 way switch

[@koushikpendyala5214]

In Gated SR latch using NOR, when E=1 and S,R =1 then you have said that the case is forbidden, but the inputs that are given are R' and S' so S,R = 0 must be forbidden? Also, The truth table for both Gated SR latch using NOR and NAND is same whereas it is different for SR latch using NOR and NAND? could you explain both these doubts.

[@aiore6369]

See the terminal brother... R output is Q not equal to R output is Q'

[@amarsinghsidhu7028]

Sir, Need derivation or source of diagram of SR latch because of confusion: Short connection from NOR gate A to NOR gate 2 vs Connection from NOR gate 2 to NOR gate 1.

[@aryansilawal6477]

you said the inputs for sr transparent latch(using nand gates) are active low inputs and others are active high inputs.does this active low or high inputs have any correlation with the outputs we get (Q and Qbar).would you clarify this. its confusing

[@ALLABOUTELECTRONICS]

No, only inputs are active low. Consider the output as it is. For example, to set Q = 1, here for active low inputs S should be 0 and R should be 1. And likewise to reset the latch, S should be 1 and R should be 0. I hope it will clear your doubt.

[@flicksonj]

can i ask a doubt? why S and R have different timing.. sometime it has very duration.. sometime low. I am not an electronics student. its my complementary sub. so do you think is there something I needed to know? the timing is 26:48

[@ALLABOUTELECTRONICS]

Both S and R are different inputs. Many times in a bigger circuits, these inputs are the output of some other circuits. So, they may not be a same. That is why, if you see a time domain signal, then you may notice that, both S and R inputs are changing at the different times. I hope, it will clear your doubt.

[@swayansamishra2284]

Hello sir at 3:56 how when S=1 then B=1!

[@ALLABOUTELECTRONICS]

Here we are assuming that, initially both S and R is 0. Now, when S is 1, then output of the first NOR gate becomes LOW. So, A = 0. And R is also 0. That means the output of the second NOR gate will become 1. And that's why B = 1. I hope, it will clear your doubt.

[@priyashalini6422]

Sir what about finite state machines kindly please do that video too

[@ALLABOUTELECTRONICS]

FSM will also be covered soon.

[@MSQ819]

i'm totally confused now

[@MdTahsinulIFayed]

How about now?

[@anuraag7075]

Same here bro

[@xiaoshen194]

5 months up... Now?

[@user-cr8zn4kx5u]

Are you alive now

[@_JODZILLA_]

He had massive ACCIDENT while studying in car... RIP 😔

[@Ranbir.Bhardwaj]

A=0 when S=high But How is B=1 when S=high @3:47

[@ALLABOUTELECTRONICS]

It is assumed that, both S and R are 0 initially. And when S becomes 1 momentarily then both A and R will be 0 and hence B becomes 1. I hope, it will clear your doubt.

[@Ranbir.Bhardwaj]

@@ALLABOUTELECTRONICS okay thank you

[@bharath_rbp]

Hello sir, Could you just explain what is active high and active low in brief? because it is getting hard to interpret these words

[@ALLABOUTELECTRONICS]

Active High means the input pin or the input signal will be active when that input is Logic '1'. (the input is active when its logic level is 'High') In the active low , the input pin or the input signal will active when that input is logic '0'. (Input is active when its logic level is 'LOW') I hope, it will clear your doubt.

[@cognitive_bits]

kuch samajh nhi aaya

[@ashikrevi]

Watch some non- indian accent. This is important to your learning too. WTF