A CPU is Only as Good as its Ecosystem: Turning RISC-V CPUs into Systems with FuseSoC- Olof Kindgren

[@volodymyrdobrovolsky8610]

The RISC-V is based on 40-year old ideas as RISC-V Foundation claims. There is no sense to port the huge x86 and ARM software ecosystems on it. Thus, RISC-V will never gain a victory over x86 and ARM. The most of positives about the RISC-V processor are arbitrary speculations. The advantage of RISC-V is open architecture. RISC-V has instructions of variable lengths. This is bad, it is a departure from the RISC architecture principles. The Contemporary microprocessors contain 8 specific hardware components: (1) SMT (Simultaneous Multithreading), (2) register renaming, (3) instruction reordering, (4) out-of-order execution, (5) speculative execution, (6) superscalar execution, (7) delayed branch, (8) branch prediction. These components make up some kind of a “magnificent eight” of components which essentially raise the performance of microprocessors. But unfortunately they are very complex. A processor core having these components is a full-fledged one, otherwise it is good for simple applications, e. g. for embedded systems. The “magnificent eight” of components is very hard to design, only the experienced firms and developers are able to do this, and much know-how was acquired, some effective solutions are patented. Particularly complex is the SMT. Only powerful and advanced firms like Intel, AMD, IBM are able to equip their processors with the “magnificent eight” components. It is not surprising that some Intel processors, and the famous Apple's M1 processor do not contain SMTs. If a company is able create the full-fledged RISC-V processor with all “magnificent eight” components then it would be a serious achievement, and such RISC-V would be considered of the World's class comparable with x86, with ARM, but not more. As far as I understand most of the developed RISC-V processors have no components from the “magnificent eight”, and are intended for embedded systems. A course directed on further development of RISC-V is a wrong way, and leads the computer architecture to deadlock. The RISC-V is not perspective for computer industry. The World demands absolutely novel microprocessor having much more higher performance than all contemporary ones. The novel and effective ideas on computer architectures do exist! Here’s such a novel processor architecture: V. K. Dobrovolskyi. Microprocessor Based on the Minimal Hardware Principle. Electronic Modeling, 2019, vol 41, No 6. pp. 77-90. The article is posted (under the Cyrillic name добровольский.pdf): www.emodel.org.ua/en/ touch ARCHIVE, then move to 2019, then to VOL 41, NO 6(2019) pp. 77-90. This processor does not have the “magnificent eight”, it is not necessary at all. This comment reflects different view on the RISC-V architecture, and the computer community has a right to become familiar with such a view. I’m Volodymyr Dobrovolskyi.

[@partitionpenguin]

Your "magnificent eight" is bullshit. First of all, do you not realize no architectures have branch delay slots anymore? How is that even a hardware component, anyway? It was only useful for simple in order pipelines. Out of order processors across the board have no reason to delay a branch, because they can just speculate on it anyway and delaying it causes the compiler to have to come up with an instruction to fill that slot with. What about a cache/memory hierarchy? Multiprocessing? Cache coherence? SIMD units? Are any of these things that any modern processor has nowadays just not worth the time? Especially the cache hierarchy. There are several OOO RISC-V implementations out there, such as the Xuantie 910. Yes, no one's taping out CPUs on the scale of Intel or AMD, but that doesn't mean that the ISA can't support it. I think RISC-V is pretty massively overhyped, but your argument is premised on the idea that you can't build a high performance OOO CPU on RISC-V, which is just not true. It's just an ISA. It does not prevent you from doing any of these things. There is nothing wrong with teaching people how to build processors with this architecture. Talks like these are pushing the ecosystem in the direction of having legitimate high performance CPUs out there.

[@cccmmm1234]

Some of those "magnificent 8" are there only to overcome the massive deficiencies in x86-like architectures. Some of them are useful in a RISC-V-like CPU, but not all. Many RISC-Vs do have some of your magnificent 8 including simultaneous multi-threading, register renaming, out of order execution, speculative execution, superscalar execution and branch prediction. Indeed RISC-V even introduced the term "harts" (rater than "cores") in the spec to support the notion of SMT (aka hardware threads). Does RISC-V really have instructions of arbitrary length? If so, it is nothing like the arbitrariness of x86 where instructions can be from one to 56 bytes long.