DVD - Kahoot for Lecture 8: CTS

[@shauryachandra2323]

I have been following these lectures and absolutely love them. It would be great if you can please record a video series of using the Cadence tools to perform FPR and CTS on a small design in real time, maybe a live stream if possible so as to get some hands on approach.

[@AdiTeman]

Hi, Thank you so much for the kind words. Indeed, I do not provide any hands on/live material at this time. This is due to commercial restrictions - both of the CAD/EDA tools and of the IP that is used (standard cell libraries). In the future, I may get permission from the two sides and work on providing such material, but this is also really dependent on my time (both to go through the bureaucracy and then to actually go and make the recordings...). And as you can probably see from the amount of material I have uploaded lately, time is something I don't have a lot of. Who knows, maybe things will settle down and I'll find the time (though I have been promising my wife that "I will have more time next month" for about 15 years :).

[@shauryachandra2323]

@@AdiTeman Thank you for the detailed response and for the incredible content you’ve already provided. I completely understand the constraints around commercial restrictions and time commitments. Your lectures have been immensely valuable, and I genuinely appreciate the effort you put into them. I have completed the DVD lecture series and I am going to start with your SoC playlist soon. If you ever do get the chance to navigate the bureaucracy and find the time, a hands-on series would be fantastic. Meanwhile, I’ll continue learning from your existing materials and look forward to any new content you can share. It would be great if you could suggest some online courses or any other references in your knowledge that could help gain this hands on experience before I actually enter the industry. And I hope you manage to find that elusive free time soon :) Thanks again, and best wishes! Regards!

[@socialogic9777]

So clock input of an ICG is a through pin and clock needs to propagate through it? Similarly all clock gating cells are through pins?

[@AdiTeman]

Yes, this should be the case. However, when you say "clock gating cells" - this is a generalization that you have to be careful with. Clock trees get very complicated and clock tree definitions can truly affect your results. For example, such a "clock gating cell" (possibly even an ICG) may be a place you want to stop the propagation of the source clock and create a separate clock tree on the output. It's very hard to generalize this and I actually have wanted to make some lecture with examples of hard/weird/non-trivial CTS problems we've had in the past, but usually I run into them in the midst of a tapeout and by the time I think about compiling such a lecture, I can't remember what the problems were (or how we solved them :).

[@socialogic9777]

@@AdiTeman Wow sir, this is an interesting example on how careful we need to be with CTS definitions and how we want the tool to interpret it depending on situation.

[@rohanyadala9096]

Very nice...

[@AdiTeman]

Thanks a lot

[@socialogic9777]

Ignore pin and stop pin related confusion : Implicit stop pin - clock will be buffered till stop pin but not beyond it. Considered for skew balancing. Ignore pin - clock will be buffered till ignore pin but not beyond it. Not considered for skew balancing. If we are buffering till ignore pin, we are balancing the skew too, then why we are saying it's not considered for skew balancing?

[@AdiTeman]

When I say "buffered", what I mean is "Fix DRVs", but not (necessarily) skew balanced. So the path until the ignore pin is ensured to meet DRVs, but it won't be considered for skew balancing vis-a-vis the rest of the skew group's stop pins.