Shift Register: SIPO, PISO and PIPO Shift Registers | What is Universal Shift Register?

In this video, Serial In Parallel OUT (SIPO), Parallel In Serial OUT (PISO) and Parallel IN Parallel OUT (PIPO) Shift registers are explained. And at the later part of the video, the working of the Universal Shift Register is also explained.
The following topics are covered in the video:
0:00 Introduction
0:40 Serial IN Parallel OUT Shift Register (SIPO)
5:44 Parallel IN Serial OUT Shift Register (PISO)
10:58 Parallel IN Parallel OUT Shift Register (PIPO)
11:50 Universal Shift Register
Serial In Serial OUT Shift Register (SISO):
• Shift Register : Seria...
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Serial In Parallel OUT Shift Register (SIPO):
In this register, the data is shifted in the register serially, but it is taken out parallelly.
Parallel In Serial OUT Shift Register (PISO):
In this register, the data is loaded parallelly in the shift register, but it moved out serially.
Parallel In Parallel OUT Shift Register (PIPO):
In this register, the data is loaded parallelly in the shift register, and it is also taken out parallelly.
Universal Shift Register:
The universal shift register has shift right, shift left and parallel load capability. Depending on the two selection line, it can be used in any one of the 4 modes. In this video, the different modes of the Universal Shift Registers are explained using the diagram.
This video will be helpful to all the students of science and engineering in understanding the different types of shift register .
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Music Credit: www.bensound.com

[@ALLABOUTELECTRONICS]

For videos on Digital Electronics, check this playlist: bit.ly/31gBwMa For more videos on Analog Electronics, check this playlist: bit.ly/3QtqdnN

[@mirnal1423]

thought this topic was quite difficult but your method of explanation made this topic a cake walk

[@godknifer]

These videos helped me pass my electronics class, thankssss😆

[@arnab94mallick]

Awesome as usual.

[@mayurshah9131]

Absolutely nice 👍👍

[@cesarcantoral6100]

Thanks for the infotainment

[@shilpapatel793]

Very nice 👌👌

[@user-dx1fc5or3t]

I would like to ask if you can share your knowledge/material that goes in depth on the mathematical modeling of piezoelectric energy harvesters. What structures could generate power at least 1uW at very low frequencies? Im writing a thesis using piezoelectric on pacemaker

[@sanjayshah9838]

👌👌👌👍👍👍

[@eda1058]

Sir, I didn't understand why we made the SIPO register like that, what was our primary goal of doing it?

[@mirnal1423]

mauj kra diye bhaiya ji kal ke exam mein aag lga denge

[@dibyojyotibhattacherjee4279]

Hello, will there be a course/series based on ece/ee/eee/in for students, based on 1st, 2nd and 3rd and 4th year pls..

[@ALLABOUTELECTRONICS]

As of now, the playlists/ series are there based on the topics and subjects. But yes, in future, will make the series based on the specific engineering year.

[@cesarcantoral6100]

Thanks!

[@ALLABOUTELECTRONICS]

Thank you, I really appreciate your support.

[@6blak197]

Why not parallel in serial out in shift left????

[@ducc1928]

Sir at 16:29 i.e during Parallel load of universal shift register what is the use of pin 0 of the rightmost mux, i mean what input is given to that ?

[@ALLABOUTELECTRONICS]

During the parallel loading, pin 0 of the right most MUX won't come into picture. Because the input at pin 3 will appear at the output. I hope you got the answer. In case, if you still have any doubt then let me know here.

[@ducc1928]

@@ALLABOUTELECTRONICS Sir but then why in 15:54 the pin 0 on the rightmost mux connected with the output of the FF 4?

[@6blak197]

4:59 have you applied the negative edge trigger to clock 2 signal i.e., upper register Coz. You said between 4 th and 5 th clock pulse we will get the output in the upper register.. Reply soon bud.

[@ALLABOUTELECTRONICS]

You can apply the clock to the upper register once the data in the lower register is settled. (After the settling time) So, here the clock to the upper register is applied between the 4th and 5th clock pulse. In this case, it happens to be after the falling edge of the 4th clock cycle.