Shift Register (SISO Mode)

[@manishpingale6558]

My teacher completely skipped the sequential logic circuits just because its hard! Your videos have helped me so much! I really appreciate it!

[@amalskumar1434]

same here🙂

[@redarabea4454]

the funny thing that made me laugh ... i openned power point for my prof. i found him putting screens of neso acadmy videos 😂 🤣

[@electronicengineering6035]

🤣🤣🤣

[@aldairzettewachenje9353]

@@electronicengineering6035 lol

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your prof belike:- send me the playlist's link, i need this

[@prathamjain5907]

Hanwate

[@vaibhavagarwal602]

Broo same xddd

[@Ankita_Modak]

I couldn't understand this topic in my college lectures but you have always been my savior .. thank youuu sir😊

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This channel is life saver for enginering students...

[@akshajsunil3322]

Sir, you sure have a great talent for teaching.thank you!

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U will always be in my prayers.. Thank you so much for helping me out with the concepts..

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best teaching channel in youtube❤️ totally love the way these ppl teach.

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better teaching than my prof..thanks a lot

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marhsall 27777 how dare you compare this GOD to your prof

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@@rohanram7197 Really This channel more helpful in this subject than my University in Europe

[@Busra-mw5xu]

I am learning English to understand the lesson. Because your teaching style is interesting and looks good

[@dheerajsolleti1854]

First of all thnx sir.I am a student of IITI and your videos were of great help.The way you explained each topic with simplicity and to the point was great. Keep it on and thank you very much.

[@pritikakumari9728]

Thanku thanku sir, this is such a best teaching style. This helps me a lot. ur teaching style is amazing, .. please provide lecture on multi vivrational circuit.

[@xenachan3479]

you saved my finals 😭😭

[@vaishnavihvvaishnavihv7305]

Thank you for helping the students from your unique and wonderful teaching and clearing the concepts ☺

[@suchetasarkar7299]

I am really grateful to you sir. Your lectures helped me a lot to understand Digital Electronics. Thank you : )

[@ritabritabasak5652]

Awesome Sir, we a Only knew, we have to do *right shift* , but why we do this, today you explained,... So lucky to have this video during my session.

[@russellandrady]

Hoy la academia de Neso me dio una gran introducción para mi conferencia. Gracias👌

[@sergejkeser7270]

Finally, I can understand what Mumbo Jumbo is talking about when he says: "Just connect a D-FlipFlop to a falling edge monostable circuit"" while building a pumpkin farm

[@nithinsai2250]

What reference is that buddy?

[@sergejkeser7270]

Mumbo Jumbo is a Minecraft youtuber. He mostly builds the so called "redstone" contraptions, which is basically a implementation of basic circuit elements inside the game. There are some people who made entire 8-Bit computers inside Minecraft

[@nithinsai2250]

@@sergejkeser7270 thanks dude

[@nithinsai2250]

@@sergejkeser7270 what is the need for a D flip flop to build a pumpkin farm?Can u share me the video :)

[@srinidhis6523]

@Prateek 🅥 see the truth table

[@rajeshwarihande4728]

my sir just tell steps but after watching your video I actually know the reason behind the concept what and why we do ...thank you so much sir

[@marinamaher8211]

your lessons helped me greatly in exam,thanks.

[@rameshadn4779]

before sem NETFLIX while sem NESO 🥶🥶

[@sadiqyt7664]

Which clg?

[@punyashloknath1990]

@@sadiqyt7664 IIT Dhanbad

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[@sandeeptiwari3655]

Love you sir....you give us beautiful lectures😇😇😇

[@billferner6741]

This reminds me on a project of years ago. It was used to create a audio echo with using serial shift registers. They called it a bucket line storage and used 8 bit wide and 1k long registers. The delay with running through those registers produced an echo effect.

[@AmitKrPaul-wq8zp]

thank you so much sir.the lecture was really helpful.can u please upload ur lectures on SIPO,PISO,PIPO,universal shift register,biderectional shift registers and buffer registers..it would really be of great help.

[@jaydwarkadhish8]

*VERYYY NICE EXPLANATION IN KZbin ONLY ON THIS VIDEO 😇😇😇😇VERY NICE TEACHING METHODS 👌🏻👍🏻🔥🔥🔥TYSM😊*

[@SunnyChopper]

Amazing video! Really helping me study for me ECE midterm right now

[@Aker]

@Prateek Patel I am guessing because of the clock it will only take the value that is current. For example when d3 receives a input and d2 will also receive a input at the same time because its a synchronous circuit so at that when d3=1, q3 has a previous 0 which transfers over to d2

[@muralisapavat1100]

Neso Academy provided the best tutorails ,good explanation thank u vvvv eee rrr yyy much

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YOU ARE A GREAT TEACHER, THANKS TO YOU I GET 100 POINTS FROM MY LOGIC MIDTERM AND WENT TO THE OBJECTION.

[@leonardopereiraamaral886]

Obrigado por este vídeo. Um estudante brasileiro agradece.

[@bhawnakukreja7589]

This was the most boaring subject for me.But because of u I m enjoying this subject now.Thnku sir u and ur way of teaching are just wonderful :-):-)

[@dharapatel8231]

i most like your speech and clear thoughts about any topics . thank you for providing this.

[@mohtasimhamidpial1705]

Thanks for this awesome lecture sir..the only reason i got good grades in my digital electronics course is due to neso academy

[@preachermarange2100]

i am really gratefull sir. you have made my life easier. thank you

[@akashprabhakar6353]

Thank u so much. Looks very simple when u teach.. Please make some more videos on ...minimization of specified sequential machines,partition techniques and merger chart methods-concept and minimum covertable.ASM- ssynthesis of output and state functions, data path,control path partition based designFault detection and locationI have seen almost all of ur videos of digital electronics and I bet no one can teach better than u. Pls pls make some more as soon as possible my exams are very near or provide me some good links.Thanku !

[@Vinayadari]

the quality of video is less but the quality of content is epic!

[@siddharth.chandani]

Explanation was great.. But You should have made separate TABLE FOR D3,D2,D1,D0.. (For better understanding)

[@Sidgo007]

true

[@hosmjrshinh2675]

U have abolish my huge unconscious doubt, thanks.

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So comfortable , so professional.

[@himanibansal1091]

You make every concept very easy. Thank you Sir

[@YandereEnthusiast]

9:31 but to get the entire output of 1111 shifted out we would need eight clock pulses right? Because we can only see Q0 as the output then after 4 clock pulses the o/p would be 1 but as we go from 4 to 8 pulses we would get 1,1,1,1 as the o/p of Q0.

[@MANIKSINGHprasad]

I think we'll need 7 clock, actually for n FFs, we need n clock for storing i/p, and (n-1) for taking o/p. So, total will be 2n-1

[@alabamaroaster1086]

good presentation of the concept thanks for the input., and finally learnt the meaning behind the concept of connecting a D-flip flop to a falling a edge monostable circuit cuz ot has been a pain to understand the fundamentals behind it for the last 2 months for me! great vid!!

[@mukeshbadigineni6361]

excellent teaching.....everyone can understand easily....

[@oguztopcu9048]

MUKESH KUMAR BADIGINENI you don’t get to decide that

[@shufflex3360]

CONFUSION......3:09 you have said that "I have already written the outputs before giving the inputs which are 0,0,0,0". Now when input was given to D3 ie D3=1, even after that you have taken D2=0 as Q3 was equal to 0, but you have given input 1 then Q3 would be equal to 1.....plz explain it

[@ugurambarc3735]

please someone answer this +1

[@vaishnavisachdeva2512]

So basically we are considering in one clock cycle the time is enough only for the new input to pass through one flipflop such that the rest take the previous outputs as inputs and not the new one

[@kartik_45]

This was just perfect by you sir!

[@moddnisha2832]

u are my sifu thanks for sharing☺️

[@keerthana.s.bidare2919]

Amaaazingggg🤩 But if you give notes also in a link or something 😅😅

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Good job.Ur an inspiration for ec brothers. Welcome to ktu.Roll back year back

[@abhijithabhi7891]

Ec brothers😍

[@meetaseth5716]

Thank u so much sir...you explained it very well....finally i understood..😅

[@21-kasthuri21]

Excellent Teaching ...... Tq

[@PrathamU-h8m]

Thank you very much🙏🙏💖

[@rahulsrinivasan7919]

Why do you always take a negative edge clock, any specific reason?

[@omalsarathg5932]

How did he draw the time sequence for Din..

[@sunilsahoosunil8142]

I am speechless this man is 💀 jod Ab me eie video mere prof.. ko dikhaunga bolunga tum bhi sikhlo💀

[@sagarrawal8332]

I was wondering when D(3) is 1 Then Q(3) is 1 , then why (D2) is not equal to 1 and that results in Q(2) is equal to 1 and similarly (Q0) is equal to 1 instantenously as these are all are connected?? why the value of Q2 or Q1 or Q0 changes only when second or third is provided to D3.

[@vinamra4893]

This happens due to delay of gates present in D-flip flop which is higher than delay caused by clk(which is a single wire).By the time o/p 1(high) of Q3 for LSB reaches D2 the clk pluse turns zero so it doesn't counts. Initially Q-3,2,1,0 are 0. When the first negative edge of clk simultaneously arrives at all input side, input at D3 at that time is 1 at D2 is 0 at D1 is 0 at D0 is 0. Same goes further cases. Hope this helps.

[@sagarrawal8332]

Thank you so much for clarification, I did thought may be it was because of master slave relation where on first it gets stored and on second pulse it shift. How wrong I was and I asked the same thing to many my friends but now I realize they have all wrong concept of it. Now it solves all and fit perfectly to puzzle. And By the way thank you so much for such nice lessons..It has helped to an enormous extent, whenever Teacher teache us and I have no idea what he is teaching....your channel always comes in my mind and take away all worries and when I came back you don't disappoint me too....Thanks one again.

[@ramgopalvarma3810]

downside up! Thank u bro

[@Mysterious_debris_1111]

@@vinamra4893 where did you learn this bro?

[@saivenkatakrishna3251]

@@vinamra4893Yaaa

[@anuhyagangavarapu]

Very nice teaching sir!!!!

[@kartikjha8197]

DEC is so easy,thanks to you.

[@facelessguy2093]

amazing videos😊😊😊

[@aprameyapadhi7782]

hows d2 = 0 in the first case because the q3 is the input for the second d flip flop

[@het314]

Exactly...

[@animeshpathak3921]

Because of clk

[@HimanshuSingh-jn1tf]

maybe because it is negative edge triggered flip flops that we are using, so the q3 changes only at the negative edge since Din=1 but at the time of clock change q3 is still 0 so there's no reason for the q2 to change as q3 changes just after the clock change

[@soumyasishbhattacharyya2805]

Because it is negative edge triggered not negative level triggered. So D2 has to wait for the negative negative edge to change its value. What I meant is that value of D2 won't change until the next clk pulse.

[@animeshpathak3921]

Well it's because of clock and I its think already explained by people below but keep in mind that dont state the reason of d2 to being 0 by stating that clk is negative edges/level triggered in exams because you can keep it positive as well , would work just the same but the graph would differ .

[@yenikacarlex484]

Thanks for the explanation but I have a question. Do we really need only N clocks for an N bit SISO register? Since we are tapping the output only at the end. Someone help me understand better

[@vinay-modem4439]

Actually 2n-1 clock pulses are required as we are taking the output at the end

[@עידו-ה1ו]

You are amazing , thank you !

[@subhasishnathdev]

thank u so much , very good tutorial , keep on posting like this.

[@moviebuff6823]

I don't really know the lsb & msb how they can be found

[@devpalwar3394]

Lsb means least significant bit (rightmost) And MSB means most significant bit(leftmost)

[@underscorebrez]

Interesting topic sire

[@dabubera4991]

Very nice video 👌 it helpful for me

[@melvinjijumathew3022]

Usually the most adjacent flipflop is the lsb but in registers the output from that flipflop is taken as msb why?

[@sujaypurakait6878]

Thank you so so much for this video. Your teaching skill is excellent.

[@BeyondDuctTapeFixItRight]

Nice presentation, clearest shift-register demo I've ever seen.

[@nishanam6683]

Siso output is take last flipflop. Q0. So after four clock pulse again 3 clock added. We get out/p is at Q0

[@ajproductions1155]

Sir can you please tell me why the clock is set down in the table?

[@Vishal-wy7re]

Sir I have one doubt. can we use positive clk pulse or not

[@sai_343]

So, for left shift we need to give Din to FF0 and take serial out from FF3

[@guliyevshahriyar]

thank you very much

[@shreyaarsewae]

Honestly speaking just because of only you I passed my exam

[@harshitahuja5043]

4:28 If Q3 is given to D2 , then it means That The value of Q3 will be given to D2 ... So why did you wrote Q3 = 1 and D2 = 0 ??? Plz Explain Plz

[@hanboliu6368]

Q and Q* are values for different times~

[@ankitbodh9272]

Thanks a lot for telling lsb would go first... my teacher confused me by using palindromes. E.g. 1001 and 101101🙂 And he told me msb would go first...

[@sourikkhan4213]

Plz... make videos on Analog To Digital Converter and Digital To Analog Converter

[@mthokozisisibanda1519]

thank you sir you have saved me

[@chesshaina]

Sir what is the meaning of downward arrow ??? In truth table...

[@abhiishekdhiman]

negative edge trigerring (falling edge of the clock)

[@trndsttr7585]

4:25 If Q3 is 1, why isn't D2 1 as well?

[@D.KrishnaPriya]

sir then what about load and clear as you told in previous lecture

[@imran22]

we are giving Q3 as 1......so D2 should be 1 rytt???.................see at @4:24...............reply ASAP

[@gautamsrivastav8330]

At 7:24 why didn't u rise at the negative edge?

[@poojasudhakar3040]

In case you have nt got the ans., still.....That is Din as in the input , in the subsequent lecture he had told that its a good practice to raise it before the negative edge just for the initial inputs(not for Q0, Q1, Q2, Q3) .That is how the system literally works.

[@yuaanrai6058]

​@@poojasudhakar3040thank you

[@sairajdas6692]

Why D becomes 1 in the middle of the clock pulse?

[@soumyashreesarangi8475]

sir u teach very nice..

[@shufflex3360]

I am confused as you are taking input and output before operating the register then again taking it after the operation

[@harithaviswanathan5655]

Thank you sir

[@saimoon4232]

Hi. Can you pls make some videos on Serial Receivers for digital logic? I dont know how to design them or the concept. Ty!

[@lhf552009]

Thanks for your presentation. It would be better to understand if you use input with the same bit. For example, 1010

[@dhananjay6171]

confusion :- why there is Q3, Q2, Q1, Q0 in output here we are using SISO , So there should be only output at Q0 ??? if i am wrong then why ???

[@srikantht2403]

thank you for your lecture

[@trishitgupta3410]

Can this siso be made using directly T flip flops?

[@josuezalazar]

So this kind of register doesn't storage any data, it only receives data and sends that data.

[@PraveenKumar-yl2hz]

If q3 is 1 then howcome you have take d2 as 0

[@sumairamushtaq3145]

sir if prest and clear inputs are in jk flip flop then what ix the output for that whn preset=0 clear=0

[@mrcastor9093]

+sumaira mushtaq The output will become unknown, unstable ( it's a shaded box until you reach the next rising or falling edge, depeding on what type of clock your flip flop runs )

[@GianlucaRoccaGian]

YOU are gonna save my grade

[@HK-qc9pp]

It could be my misunderstanding , But doesn't it seems to be a parallel output because serial output is made of more than one bit. please someone correct me.

[@prasanjitrath281]

Late reply but might be helpful for others: The above video gives parallel output only, if you observe Q0 then you will see that after 4 pulses, it contains only the LSB, so you need to give another 3 pulses to shift the remaining bits to Q0.

[@AnoNymous-po5sx]

@@prasanjitrath281 Right! I just checked again and found that even if we give 3clock pulses extra, the data we're getting in serial form is in reverse order. I took 1011 as an example, the order I got is in reverse. Please clarify.😐

[@prasanjitrath281]

@@AnoNymous-po5sx That is happening because you are feeding the left most bit first to register, so you are getting 1101 for 1011 input. So, if consider your example as 1011, just start feeding the MSB first and then go towards LSB.

[@AnoNymous-po5sx]

@@prasanjitrath281 Yeah I got it. Thank you! 😁😁😁