Shift Register (SISO Mode)

Digital Electronics: Shift Register (SISO Mode)
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Hanwate

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[@AmitKrPaul-wq8zp]

thank you so much sir.the lecture was really helpful.can u please upload ur lectures on SIPO,PISO,PIPO,universal shift register,biderectional shift registers and buffer registers..it would really be of great help.

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My teacher completely skipped the sequential logic circuits just because its hard! Your videos have helped me so much! I really appreciate it!

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Hoy la academia de Neso me dio una gran introducción para mi conferencia. Gracias👌

[@alabamaroaster1086]

good presentation of the concept thanks for the input., and finally learnt the meaning behind the concept of connecting a D-flip flop to a falling a edge monostable circuit cuz ot has been a pain to understand the fundamentals behind it for the last 2 months for me! great vid!!

[@billferner6741]

This reminds me on a project of years ago. It was used to create a audio echo with using serial shift registers. They called it a bucket line storage and used 8 bit wide and 1k long registers. The delay with running through those registers produced an echo effect.

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Thanks for this awesome lecture sir..the only reason i got good grades in my digital electronics course is due to neso academy

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[@sadiqyt7664]

Which clg?

[@SunnyChopper]

Amazing video! Really helping me study for me ECE midterm right now

[@Aker]

@Prateek Patel I am guessing because of the clock it will only take the value that is current. For example when d3 receives a input and d2 will also receive a input at the same time because its a synchronous circuit so at that when d3=1, q3 has a previous 0 which transfers over to d2

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better teaching than my prof..thanks a lot

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marhsall 27777 how dare you compare this GOD to your prof

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@@rohanram7197 Really This channel more helpful in this subject than my University in Europe

[@himanibansal1091]

You make every concept very easy. Thank you Sir

[@preachermarange2100]

i am really gratefull sir. you have made my life easier. thank you

[@omalsarathg5932]

How did he draw the time sequence for Din..

[@rajeshwarihande4728]

my sir just tell steps but after watching your video I actually know the reason behind the concept what and why we do ...thank you so much sir

[@subhasishnathdev]

thank u so much , very good tutorial , keep on posting like this.

[@sergejkeser7270]

Finally, I can understand what Mumbo Jumbo is talking about when he says: "Just connect a D-FlipFlop to a falling edge monostable circuit"" while building a pumpkin farm

[@nithinsai2250]

What reference is that buddy?

[@sergejkeser7270]

Mumbo Jumbo is a Minecraft youtuber. He mostly builds the so called "redstone" contraptions, which is basically a implementation of basic circuit elements inside the game. There are some people who made entire 8-Bit computers inside Minecraft

[@nithinsai2250]

@@sergejkeser7270 thanks dude

[@nithinsai2250]

@@sergejkeser7270 what is the need for a D flip flop to build a pumpkin farm?Can u share me the video :)

[@srinidhis6523]

@Prateek 🅥 see the truth table

[@ritabritabasak5652]

Awesome Sir, we a Only knew, we have to do *right shift* , but why we do this, today you explained,... So lucky to have this video during my session.

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Thank u so much. Looks very simple when u teach.. Please make some more videos on ...minimization of specified sequential machines,partition techniques and merger chart methods-concept and minimum covertable.ASM- ssynthesis of output and state functions, data path,control path partition based designFault detection and locationI have seen almost all of ur videos of digital electronics and I bet no one can teach better than u. Pls pls make some more as soon as possible my exams are very near or provide me some good links.Thanku !

[@sujaypurakait6878]

Thank you so so much for this video. Your teaching skill is excellent.

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DEC is so easy,thanks to you.

[@Haax06]

Hi Neso, what happends if not all bits you want to store is the same, for example "1010" ?

[@dheerajsolleti1854]

First of all thnx sir.I am a student of IITI and your videos were of great help.The way you explained each topic with simplicity and to the point was great. Keep it on and thank you very much.

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[@RickSaffery]

Nice presentation, clearest shift-register demo I've ever seen.

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So comfortable , so professional.

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thank you for your lecture

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U have abolish my huge unconscious doubt, thanks.

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Thank u so much sir...you explained it very well....finally i understood..😅

[@alaagalal4046]

Thanks for your Teaching ,It Is very smart and great but i have a question IS it support shifting any number in 4-bits for example 1100 ?

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This was just perfect by you sir!

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please give the link to previous and next video in the description

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excellent teaching.....everyone can understand easily....

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MUKESH KUMAR BADIGINENI you don’t get to decide that

[@kawaiineko5439]

does the siso register store this data for long and whenever we want the output we request it, or the output comes out as soon as the signal is applied? if it's the second case then what would it benefit us if the output signal is equal to the input but just delayed by few micro-seconds?

[@amanjain256]

Should the FF's be positive edge triggered or negative edge triggered?

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You are amazing , thank you !

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[@keerthana.s.bidare2919]

Amaaazingggg🤩 But if you give notes also in a link or something 😅😅

[@siddharth.chandani]

Explanation was great.. But You should have made separate TABLE FOR D3,D2,D1,D0.. (For better understanding)

[@Sidgo007]

true

[@masterchef8671]

can the clock be positive edge triggered??? will anything change then!?

[@ashiteygabriel7852]

how do you draw SISO register circuit with a positive edge triggering clock pulse using D flip flop

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*VERYYY NICE EXPLANATION IN KZbin ONLY ON THIS VIDEO 😇😇😇😇VERY NICE TEACHING METHODS 👌🏻👍🏻🔥🔥🔥TYSM😊*

[@anuhyagangavarapu]

Very nice teaching sir!!!!

[@kemthursuraj6600]

Thank you a lot!!

[@yenikacarlex484]

Thanks for the explanation but I have a question. Do we really need only N clocks for an N bit SISO register? Since we are tapping the output only at the end. Someone help me understand better

[@vinay-modem4439]

Actually 2n-1 clock pulses are required as we are taking the output at the end

[@IsraeliFisherman]

Very very good. Thx a lot

[@abiral_neupane4045]

my dude thank you soo much

[@sumairamushtaq3145]

negative edge tigger and positive ege hav no differenc? only that wrkng dpnd on that tiggering?

[@YandereEnthusiast]

9:31 but to get the entire output of 1111 shifted out we would need eight clock pulses right? Because we can only see Q0 as the output then after 4 clock pulses the o/p would be 1 but as we go from 4 to 8 pulses we would get 1,1,1,1 as the o/p of Q0.

[@MANIKSINGHprasad]

I think we'll need 7 clock, actually for n FFs, we need n clock for storing i/p, and (n-1) for taking o/p. So, total will be 2n-1

[@muhammadidreeshassan8415]

Sir What about Shift control registerS? Do you have any lecture on this topic?

[@and1fer]

Thank you very much Sir.

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This was the most boaring subject for me.But because of u I m enjoying this subject now.Thnku sir u and ur way of teaching are just wonderful :-):-)

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Excellent Teaching ...... Tq

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thank you!!!

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thank you sir you have saved me

[@guliyevshahriyar]

thank you very much

[@suparatyongjoh5642]

Thank you so much

[@haneenal-ali1571]

is shift register is always contain of 4 delay flip flop?? or the number of delay flip flop is depend on the number of bit of input date

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[@saimoon4232]

Hi. Can you pls make some videos on Serial Receivers for digital logic? I dont know how to design them or the concept. Ty!

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Good job.Ur an inspiration for ec brothers. Welcome to ktu.Roll back year back

[@abhijithabhi7891]

Ec brothers😍

[@Trueheartedtrupti]

If the data to be stored is 1010 then how ll be the graph

[@shakthivelcr7]

IF D3 is given as 1, shouldnt the output, i.e Q4 be iving out 1? why is it 0? please help.

[@prajwalbhati2101]

This happens due to delay of gates present in D-flip flop which is higher than delay caused by clk(which is a single wire).By the time o/p 1(high) of Q3 for LSB reaches D2 the clk pluse turns zero so it doesn't counts. Initially Q-3,2,1,0 are 0. When the first negative edge of clk simultaneously arrives at all input side, input at D3 at that time is 1 at D2 is 0 at D1 is 0 at D0 is 0. Same goes further cases. Hope this helps.

[@soumyashreesarangi8475]

sir u teach very nice..

[@ruoyuzhi3549]

Why do the values change at falling edge of clock? Isn't D flip flop a positive edge-triggered device?

[@dabubera4991]

Very nice video 👌 it helpful for me

[@nishantsubedi6620]

Do anybody knows in what board or app or something that he is writing

[@sulakshana238]

thank you... your videos have been very helpful

[@KhangNguyen-kl9nx]

thanks so much !

[@mdmahmudulhasan6448]

I love you bro!!

[@trishitgupta3410]

Can this siso be made using directly T flip flops?

[@Fitnesswithankit1]

Thank u so much sir

[@minxxdia1132]

i finally understand how this works. yay! thanks to you..

[@ankanbrahmachary6581]

Can anyone please tell me why did the din becomes high just before the 1st falling edge???? Please it's urgent

[@abhishekhinba]

is this unidirectional shift register ?

[@pratikagarwala2919]

Why are you using negive edge triggering everywhere? Is it to remove glitch?

[@harithaviswanathan5655]

Thank you sir

[@GianlucaRoccaGian]

YOU are gonna save my grade

[@fatimamirza9510]

How do we do the shift left mode?

[@murtazahussain6301]

pass the msb first

[@facelessguy2093]

amazing videos😊😊😊

[@DevendraSingh-bk7sv]

thank u so much sir.....

[@prakashb1278]

thank you.!!

[@naoexiste7809]

Bom dia, em meu projeto pretendo ligar um sensor de cor ao shift, como eu faço para declarar as variáveis dos pinos do sensor que estarão ligados ao shift?

[@user-bu8mg7uq3s]

thank you

[@pratimamodi607]

sir what about shift left mode???

[@asimraja6142]

one thing i dont understand why negative edge trig clock is given??? and how the circut operate for +ve edge trig clock ....Can you answer plz