An Introduction to Verilog

Introduces Verilog in less than 5 minutes.

[@aaroncameron1494]

This short 5 minute video is the best available on verilog

[@theguywithamustache3974]

Dude even after 7 years i would agree to that

[@yugandharreddy1507]

Yes

[@TheBest-zi2fp]

After 10 years still holds true

[@akaras250]

The best video about verilog for beginners out there!! I' ve seen many of them that are 20-40 minutes long and i couldn't understand a single word. Great work bro!!!

[@bonvivant8618]

One of the best video got so far, clear, crisp..

[@nathanielsicard]

I have been searching for this exact video for three days you are an absolute lifesaver thank you

[@dave_dennis]

Very well organized! This is the most coherent description I've found. Thanks!

[@eggbertherman100]

excellent. absolutely excellent! Love the simplicity in the explanartion and the straight fordwardness

[@Alan-lm9no]

Pretty intuitive, this should be the best Verilog introduction video ever.

[@vincentgao8660]

the best video about Verilog, the vlogger is smart for sure.

[@salmansyed9962]

This video is the BEST way to understand a whole frickin topic in 5 mins. Literally the best video for beginners

[@XTDHHARRYCX]

Sir, thank you so much! Your video was not only helpful but gave me an excellent start to my verilog learning experience.

[@raypol1]

Excellent video ! I been trying to learn verilog for a while and this really helped me understand it better.

[@bibhakardas5761]

Shortest, simplest and best explanation on Verilog!

[@mahabuburrahman1160]

This is the best organized video........take love

[@mingenwu4008]

The quickest video to understand what the Verilog is. Thx.

[@bikashpandey4051]

This video is the best video about verilog which i understood clearly.

[@sususu9]

even after years still the best. bless your soul

[@balramsharma5887]

waw...superb teaching technique....thank u

[@SandeepKumar-ls6li]

Simple and on the point! Best explanation

[@habibkazemi5132]

The best verilog tutorial I ever seen :)

[@arifnishan5646]

best video i found for verilog. More please

[@SuperShafi2010]

Excellent explanation thanx

[@YeMariam828]

Thank you so much it simplifies the core of understanding Verilog with in 5 minutes👏

[@akhilhooda740]

RESPECT BROTHER !!! 4 min video>>>>prof's 1 hour lecture

[@SureshBabu-lk7cm]

Sir I am beginner simple study and systematic way cleary explain.thanks lot

[@harsh__nasit]

Woah man! Thank you so much!!! 😊 Really appreciate your efforts!

[@ziangtian]

Amazingly concise and so beginner-friendly

[@ilak9806]

Thank you for your simple and understandable video.

[@elmerosorto1680]

Thanks for solving my doubts about verilog

[@PibuFilms]

amazing, love the quick bite info style tysm

[@fenghc1]

Very concise and clear description!

[@jayeshswami5207]

This video will definitely save my test *peace*

[@nileshbaldaniya9419]

very easier beginning for learner. thankyou sir...

[@HK-no9wm]

extremely well explained. Thank you sir :)

[@DrewCottrell]

Exceptionally good intro. Nicely done.

[@devasish_]

awesome 5 minutes of my life searching here and there for verilog basics

[@statha3624]

Wow this was super helpful!!! Thank god i got to this before my exams came up

[@insider7649]

😂😂I watched 4 videos on verilog ,and this single video explained content of those 4 videos. Superb explanation.

[@fteiyp]

you're a legend mate

[@sfndude1768]

This is the best short video for verilog basic

[@pupw5519]

Great video, I learned more about verilog!

[@shivashankar28]

Beautiful !!! The world needs more FPGAs

[@JackIsNotInTheBox]

THANK YOU! The visual aids helped alot!

[@akshaynadig1893]

Really wonderful expanation ..

[@tahsinalmahi8769]

Thanks! Excellent explanation.

[@laadugaming6535]

Excellent bro.. ❤️👑

[@yangzhou9548]

such a great explanation, thank you

[@varunb9777]

Best video for beginners.

[@yunosimi7170]

You know what KZbin, next time put this video as the first suggestion for Verilog. Not some company videos nobody will easily understand.

[@a7med7asan151]

Amazing Video ! Btw, Really shocked when i knew that Verilog does not describe bedrooms :"D

[@saudk9261]

Great short description of Verilog

[@michaelscience2481]

You just crushed it bro.

[@it154-sonineel9]

Best Video Ever U seen About Iverilog

[@user-ik9th1nk9n]

Thank you so much . You are awesome!!!

[@ibemper1850]

even though it isn't a programming language, it is very similar to object oriented languages class -> module wire -> variable module adder(o,x,y) -> constructor this is very similar to c++. your explanation is amazing!! thanks for putting in so much effort

[@jiaqixiu6037]

Thanks ! Your explanation was clear !

[@dupajasiu920]

great start, I wish there was a full course

[@harvey2355]

Sir your explanation is best you should must make more videos on verilog as well as system verilog and UVM

[@companymen42]

You sir a amazing! I thought they only taught VHDL in the midwest, but I guess I'm wrong.

[@tukkinum]

Oh my God. Thank you. Seriously

[@sofiabuchelnikova4143]

Wow, now I understand what Verilog actually is, thanx!

[@nikosnikolakis6991]

it tok me exactly 5 mins to understand . nice job

[@saurabhsinha8779]

this is awesome... sir

[@SaadShah1133]

Very well presented ...

[@shehzadkhan7570]

Amazing Video Sir! Kindly make such a video on VHDL

[@mzshmkn]

Okay, this was amazing. Thank you

[@chrishadjipetris6059]

This video refers to structural hardware description, but hardware description languages also provide rtl description

[@williesolomon614]

Very well explained. Thank you. Can you make more ruboost tutorial about Verilog.

[@Live4Ibanez]

Excellent video

[@saidulislamsayem9278]

Awesome!!! Thanks a bunch!!!

[@xxw6371]

impressive and informative!

[@agstechnicalsupport]

Very good introduction to Verilog !

[@furkanunsal5814]

as a computer science student I was researching about vhdl, after around 10 hours of reading and watching I decided to check how verilog works and found this video. I think I might want to learn verilog instead.

[@MustafaTULU32]

Thanks, It was very clear.

[@smartway6992]

superb video thank you thank you thank you so so much :D

[@mohammedalsaeedi9417]

Best video for verilog

[@something2493]

This is amazing!

[@stevewong7066]

amazing video

[@TheLogicalGigabyte]

Fantastic, thank you!

[@taneravci6808]

Nice video, do more

[@perceptrongaming4290]

that was great !, dont u have a playlist on verilog coding /xilinx ??

[@yusrymahmud6872]

can we use assign statement? for example assign or_wire= x|y ; assign not_wire= ~y ; assign o=or_wire & not_wire ;

[@NateJohnsonMusic]

Best video ever

[@mubasheer5584]

Wow an amazing way to explain such sensitive language for the dumbs like me.. Please give me more links of your video I wanna learn whole RTL from you.

[@anaformiaabalatusdispositi4769]

Very good introduction, thanks. It somewhat begs the questions "wires?". Why not do it in the proceedural way of simly passing the output of one function (module) into the input of another? Having the wire declared independently looks like it can cause problems.... surely it allows you to have the one wire as the output of more than one module? Why have a language grammar which allows you do that by having a wire exist as a seperate entity to the inputs and outputs? Whilst a wire is exactly that in the real world... independent of the circuits you put it in... in the world of circuit design you don't want wires to be floating around on their own.

[@jyotirai4714]

why are you stopped making videos on verilogs, its so nice with great and relateble examples

[@ssnlp44]

excellent...

[@sneaky_noodles]

Been reading websites about Verilog. Why can't websites explain any clearer like your videos. Thanks!

[@kabandajamir9844]

So nice thanks

[@DavidWongTianyu]

really cool video, thanks :D

[@saurabhsinha8779]

plz make more videos..

[@petercheung63]

very good, thanks

[@hansoflaherty9864]

Awesome

[@subhrajeetdas2698]

best one

[@chenmichael569]

AWESOME!

[@ericling3536]

Thank you so much!!!!!!!!!!!

[@mridulverma1392]

thnx for adding this

[@aminabukoash9456]

beautiful

[@RegenerationOfficial]

It's like PLC languages when they were more basic than they are now. My favorite since I was trained using S7 with LOGO!, a Click and Drag Logic Gates and Compile, is FBD (Function Block Diagram). How far am I from machine code or is it really not so advanced for stability’s sake? In that regard, my favorite quote is : "If I would deliver code like the folks from windows do, I would lose my job immediately"

[@abdisamadjoe]

Thank you bro

[@kevinpatzer1551]

GREAT!