Verilog Basics

[@marcellvarbai6264]

This is so amazing. Your lesson was perfect,good job. Thank you

[@maripaz5650]

This cleared up a week's worth of confusion, thank you!!

[@hazalberilcatalak4477]

i learned some main ideas of verilog as a molecular biology and genetics undergrad, for understanding some synthetic biology coding. thank you.

[@chrishadjipetris6059]

There's another way to implement the foo function. You can also do it like this: always @(a or b or c) case (a) 0 : foo = b | c; 1 : foo = b ^ c;

[@GloomyHouse]

I wonder if I fed my dog today.....that being said....thank you for the presentation. Very Helpful !

[@gregorymccoy6797]

Lots of questions but this was very useful. Thank you.

[@paulfranzon2229]

Kevin: You need the begin and end if there is more than one statement following the always trigger.

[@rolfw2336]

There might be a problem at 6:15, where variable a is not defined. Otherwise, thanks, very helpful.

[@ShreyasBharadwaj]

My whole semester of learning didn't make it as clear as this short video

[@paulfranzon2229]

The quizzes are in our learning management system and not publicly accessible. Thanks for your interest.

[@brindamavadiyan8972]

Great work looking for more videos

[@TooSlowTube]

I need to come back to this once I understand what kind of assignment that is (

[@paulfranzon2229]

This is covered in the full class playlist in the Verilog 2 section. Thanks for watching and the comment.

[@TooSlowTube]

@@paulfranzon2229 That's good. Thanks. When you mentioned the full course, I thought you meant as you'd taught it to your students, but that it wasn't covered in your KZbin videos.

[@paulfranzon2229]

@@TooSlowTube The full course can be found at kzbin.info/aero/PLfGJEQLQIDBN0VsXQ68_FEYyqcym8CTDN . This is covered in the Verilog2 section.

[@TooSlowTube]

@@paulfranzon2229 Excellent. Thanks, Paul.

[@priyanks91]

Thank you very much

[@amritpalsingh3293]

For what b are used for and why D has not been declared as an input?

[@carinezXz]

Thank you very much this is useful for beginners like me..:)

[@PYC1337]

if you use switch cases or if statements the cpu will take more time figuring out whether the imposed condition is true or false, i am fairly new to verilog but i've learnt C, embedded C and assembly, so i was wondering, can you use decoders or encoders instead of MUXs and DEMUXs in order to avoid conditional statements?

[@paulfranzon2229]

decoders and encoders are still coded using case statements.

[@hazimaznan2077]

Thank you very nice video

[@dilaracoban7467]

thank you

[@raaami007]

its Very clear for me now , thank you sir

[@6s6]

Is it really necessary to have the begin and end in the verilog module for flipflop?

[@ianthorp900]

very helpful, thank you!

[@rajaposupo8376]

Thank You Sir....

[@Easylife_120]

What is difference between Standard verilog, power verilog and fast verilog?

[@sunshinekanika5797]

i cant find this link mentioned in the video .. showing error 404

[@Submersed24]

My professor is having us write a decoder in Verilog, and I understand the code, but I can't find a single example of how to compile the code or what the output of the code is supposed to look like...

[@paulfranzon2229]

You need a synthesis tool. You can download the student version of Quartus from Alterra (now Intel) for free.

[@anamaykane9355]

@@paulfranzon2229 Hello Paul. Is there any way I can access the sub module quizzes mentioned by you in the Digital Design online course? That would be very helpful. Thanks in advance.

[@pamp3657]

Good fucken video thank you sir

[@althafyoosuf9987]

very good lecture,... thank you sir

[@fluffysesshyandrin]

thank you very much!

[@ComradeChrome]

The constant clicking in the background made if very hard for me to follow along to this otherwise good video. I have ADHD though, so maybe others weren't so bothered.

[@paulfranzon2229]

I must admit I dont know where the tapping comes from. Possibly its some artifact introduced along the way, possibly by the audio compression in Camtasis.

[@samhsmith]

Very good

[@hyalzaq]

Thank you.

[@AJ-bj5ds]

Sir, Can we convert a C language code into verilog .

[@paulfranzon2229]

Not very efficiently

[@kaiser_michelle]

Thanks!

[@tlogan404]

Dead link... :(

[@venkatesh.venky0805]

yes

[@yasmeen2173]

hello have you an email can l contact with you ? because I have a project and I need to help to do my project please. my project can make by verilog language

[@paulfranzon2229]

A search engine turns me up. My affiliation is clear from the slides.

[@yasmeen2173]

@@paulfranzon2229 thanks🌸 I send you an email I hope to help me please

[@Tapajara]

IMHO: Real hardware is continuously evaluating an expression, not just when the inputs change.

[@tech4allbyshameer502]

👍👍

[@asfandyarsanam8807]

Sir thank u

[@himanshu6489]

why u people pronounce code(which is "kode") as "khode"

[@SmartShocks]

Himanshu Doley Dear sir, he is trying to teach you something important. Don't ask stupid questions about his accents!

[@ZweiSpeedruns]

the k and aspirated k sounds are interchangeable in english, to the point where many native speakers can't tell the difference unless it's exaggerated.

[@donpasquale8486]

What are you talking about? He's pronouncing it with his British accent what's your problem lol? Your accent is a lot worse for pronunciation, so I wouldn't be talking if I was you, at least his is one native to the English language.

[@AverageMinion98]

Cover (kover) as khover

[@migkillerphantom]

Not everybody is a poop-juggling street shitter like you bro

[@amritpalsingh3293]

For what b are used for and why D has not been declared as an input?

[@paulfranzon2229]

b is an input do this module. D is not since its the ouput of a gate inside the module (a mux.)