Analog VLSI Design Lecture 24 Part 1: Cascode Current Mirror circuit

AVLSI lecture 24 part 1 covers the following topics:
1. Need of Cascode Current Mirror
2. Journey towards building Cascode Current Mirror
3. Cascode Current Mirror analysis
4. Cascode current mirror sizing requirement
5. Minimum allowable voltage at node P
‪@InderjitSingh87‬

[@santali_IITians]

What an explaination .... Best video for Analog design

[@fidelcertuche8002]

Thank you!!!

[@jiteshnayak7338]

Really helpful video sir would be really helpful if you could provide the onenote links too or the pdfs of the lectures

[@renukaatri1206]

Superb efforts and great content . Atleast you are helping vlsi student a lot . Thank you sir plz keep uploading .

[@InderjitSingh87]

Thank you, I will

[@renukaatri1206]

@@InderjitSingh87 sir can you plz make a vedeo on wilson current mirror and super wilson current mirror simulation . How exactle we have to balance it like w/l ratio, vgs matching etc.

[@InderjitSingh87]

@@renukaatri1206 Sure, I am occupied currently with work, will upload soon.

[@gean7917]

Very helpful. Thanks a lot.

[@InderjitSingh87]

You're welcome!

[@shohebkhan4045]

beautiful explanation sir . i was having so much confusion in modified Wilson current mirror, that u just resolved in blink of 30 mins

[@InderjitSingh87]

Glad to hear that

[@vaibhavkapadia1]

amazing explanation.

[@InderjitSingh87]

Glad you think so!

[@camerondeanda5533]

This was explained very well while explaining assumed idealogies other videos don't mention!!

[@InderjitSingh87]

thank you, glad it is helpful.

[@nutboy2676]

Your handwriting is amazing.

[@InderjitSingh87]

thank you!

[@dazzlingkiller7002]

Where can I get ur written notes ??

[@harishmacharla1863]

Clean and neat explanation sir. Thank you sir Where can I find these handouts ?

[@InderjitSingh87]

thanks Harish, handouts aren't available currently. You can take notes from videos itself.

[@shirsenduacharyya9443]

Sir plz take the current mirror circuit in Electric Vlsi tool and simulation in LTSpice , I find it very difficult to get a proper simulation result

[@InderjitSingh87]

yes sure, will try

[@onelivingsoul2962]

Hi sir,you arrived at the correct result but your train of thought is incorrect. Why Vgd3=0? and whats with this Vp+Vth and Vq-Vth? The correct way of thinking is Min voltage at X is VGST1 +VT1. The extra VGST is for it to drive current Iref through M1, similarly at point Q, min of VQ is VGST0+VT0 +VXmin=VGST0+VT0+VGST1+VT1 Now due to current mirror action by M3-M0,M2 is ensured to be in saturation as Vy follows Vx,hence in saturation.(only if Vp>VT+VGST) So now for M3 to be in saturation VPmin=VQmin-VT3 so if all VT are same,we can rewrite the equation as VPmin=VGST0+VGST1+VT you can sort of plot it as Iout vs Vout and see post Vpmin the Iout flattens out.

[@poojadhankher2666]

Sir, Here Vp is only 2 overdrive , R.H. and L.H.S both have Vth term.Kindly check.

[@InderjitSingh87]

Its point j, yes both sides have Vth added deliberately to balance, then VQ -Vth is equal to Vp +Vth, in reality this Vp + Vth is conventionally Vp voltage which is equal to VQ + Vth, so that why Vth is added to Vp.

[@srinidhigunjikar6144]

Sir, In the minimum allowable voltage at Node P calculation section, for M3 to be in saturation, how did we arrive that VGD3 should be 0?

[@InderjitSingh87]

VGD3 = VGS - VDS = 0 means, VGS is always greater than VDS, meaning M3 is in saturation

[@aminewa500]

​@@InderjitSingh87why you didn't use Vds>Vgs-Vth so Vd>Vg-Vth so Vgd

[@jayaprakashchennoju4309]

Sir can u provide pdf of AVLSI course

[@InderjitSingh87]

Notes are not available. I always encourage learners to note down important concepts from the video. That will be your notes.

[@aamir99204]

Sir why vgd3 =0?

[@InderjitSingh87]

VGD3 = VGS - VDS = 0 means, VGS is always greater than VDS, meaning M3 is in saturation

[@dazzlingkiller7002]

Can you please send the written notes please 🙏🙏🙏 please

[@InderjitSingh87]

Notes are not available. I always encourage learners to note down important concepts from the video. That will be your notes.

[@nehauk9314]

How VX= VDS1

[@InderjitSingh87]

In case of MOSFET M1, its Gate and Drain terminal are tied together, and Source terminal is grounded, Assuming body is also connected to source, now VGS1 = VDS1, and VX is measured between Drain and ground i.e VDS1 itself, thats why VX = VDS1 = VGS1

[@dazzlingkiller7002]

Can you please send the written notes please 🙏🙏🙏 please

[@InderjitSingh87]

Notes are not available. I always encourage learners to note down important concepts from the video. That will be your notes.