SERDES LAYOUT (WIRE / INTERCONNECT PARASITICS)

[@mohdkhairizulkalnain279]

Nice lecture! Looking forward to one on DFE and TX Equalization techniques.

[@analoglayoutdesign2342]

Thanks for the feedback.Sure will post them as well

[@張鈞堯-h4m]

Agree !!!

[@sivaiahnaali459]

Good contet in lecture sir and we'll explained👍. If possible please provide more videos on high speed serial links.

[@meghachandargi6805]

Thank u sir for the wonderful content!!!

[@goldeneye111ful]

Thickness is dependent on the metal stack options for that particular node..as we go to lower geometry process ..thickness also has to decrease..

[@analoglayoutdesign2342]

That’s what .. thickness will also reduce but comparable to distance between the metal lines.. Hope you got what I meant

[@smuchini]

Great lecture with clear examples. Can you share the part2 of this topic pls? Thanks.

[@analoglayoutdesign2342]

Thanks Sanjay for the feedback. I will record part2..need little time.

[@lilwiterose]

You are awesome!! You make great content to learn from. Easy concepts and examples. Thanks a lot!

[@xuli3400]

Thank you Sir for the lecture! It is very helpful. Just wondering if there is a plan to teach the part2 in the outline (inverter input and output parasitic capacitance, and propagation delay)

[@analoglayoutdesign2342]

Yes plan is there for part 2. Inverter parasitics..

[@gotoysuresh]

Thank you for good lecture sir! I have one question on parasitic resistance. As you know resistance increases with frequency due to skindepth. For SERDES, operates are in GHz range, don't you think per sqaure sheet resistance is under estimate of parasitic resistance ? Would this be significantly higher ?

[@analoglayoutdesign2342]

True… resistance due to skin effect needs to calculated…

[@anusharao7500]

You have explained about parasitics calculations but can you please explain me how it effects that signal? and how that leads to circuit degradation?

[@analoglayoutdesign2342]

Yes.. will prepare one more video to add all delays and how maximum speed of operation gets affected

[@sunkarasaigoutham]

Hi Jay, May I know which company you work for? Thanks, Sai.

[@veereshj1916]

Hi thanks to your videos...can you please make videos on EM/IR and how to calculate it, antenna, lod, sti topics.

[@analoglayoutdesign2342]

sure...EM/IR and Crosstalk and line delay will be first few.....

[@jhansilakshmi80]

Hi Please provide video on ring oscillator waiting for current mirror part2 andsub 1V BGR

[@analoglayoutdesign2342]

Sure...will take little time..little busy with work...but will surely upload..

[@sunkarasaigoutham]

Also waiting for your sub 1V BGR video :)

[@bhavanireddy1152]

Please make a video on ADC PROJECT ????? ND MORE VIDEOS ON FINFET ????

[@analoglayoutdesign2342]

yes...ADC DAC is pending..will do that...but FinFet will come before that...

[@bhavanireddy1152]

Thankyou

[@shwetakundgol6468]

Hi sir When you'll post matching techniques and op amp operation videos

[@analoglayoutdesign2342]

I will post for 5 transistor OTA...will that help? Which one are you looking at?

[@shwetakundgol6468]

@@analoglayoutdesign2342 I was looking for part 2 of current mirrors video which you posted. I'm also looking for opamp design and operation

[@analoglayoutdesign2342]

@@shwetakundgol6468 ok will post it

[@shwetakundgol6468]

@@analoglayoutdesign2342 ok thank you

[@hemantpise3414]

can you give me the classification about 2nd order effect and short channel effect

[@hemantpise3414]

because when search in both showing same effect

[@analoglayoutdesign2342]

yes...will upload videos

[@hemantpise3414]

Thank you , but make as early as possible

[@analoglayoutdesign2342]

@@hemantpise3414 sure

[@Nandamashok]

scripting languages videos for vlsi

[@alterguy4327]

Any scripting language works fir VLSI. You should have a strong base on REGEX and File handling etc