The 300mm Silicon Wafer Transition

[@johnmurray3888]

So nice to listen to a narrator who gets straight to each point without the tautology, irrelevance, and fuzziness that beset so many KZbin presentations.

[@lawrenceperson3043]

I worked at Applied Materials during the transition, and one thing you didn't mention that delayed the transition to 300mm was the introduction of copper rather than aluminum interconnects starting around 1997. This blindsided much of the industry, and the cost to transition to copper soaked up much of the money that would have gone to the 300mm transition otherwise.

[@Shaker626]

As I understand it, aluminum is a p-type dopant whose diffusion becomes a problem at smaller nodes, correct?

[@lawrenceperson3043]

@@Shaker626 Aluminum isn't a dopant, it's an interconnect. P and N type dopants are used to build the actual logic gates. Boron is the most common P type dopant.

[@giuseppebonatici7169]

@@lawrenceperson3043 I think that weeb destroyah means that aluminum can displace silicon and can act as a p-type dopant. I makes sense to me, but I'm a geologist, so I am well acquainted with aluminum replacing silicon in silicates. I lack specific knowledge to know if it is possible in metallic silicon through diffusion while making the interconnect.

[@soren6045]

Metalls a poison for semiconductors. Copper diffuses much faster. One of the challenges for copper integration was to find a good barrier. The advantage of copper over aluminum is a lower electrical resistance and much lower electromigration.

[@Shaker626]

@@lawrenceperson3043 I meant to say that aluminum can act as a p-type dopant in terms of a contaminant, not a deliberate dopant. But that would be the main reason copper was chosen over aluminum, right?

[@E100Omega123]

our company still produces 200mm wafers. Everyone keeps talking about transitioning to 300mm. But literally everything we have on hand is geared to 200mm, from shipping boxes to tools. Interesting video. Thanks!

[@Gameboygenius]

Interesting. Which process node are you on? I would've thought legacy nodes might still use 200 mm.

[@E100Omega123]

@@Gameboygenius Dont know too much about the production process. Just that we make 200mm

[@gg-gn3re]

​@@Gameboygenius places that deal with wafers don't even do that part. It's a different section entirely. Many chips 130nm - 28nm are still using the 200mm wafers though. This is where the biggest shortage is as many whom watch these videos probably know. Too many people think "chip shortage" = desktop CPU but those have the least problems. all the tiny micro controllers etc are on 28nm or bigger and 99% use 200mm wafers, mostly because the finfet has way too big of a failure rate to waste it on those types of chips, so 28nm is the smallest they go. This is also why the chipsets of many motherboards are still like 28-40nm

[@Shaker626]

@@Gameboygenius SOI, power transistors, SOS, mixed signal and legacy nodes to name a few. None of these rely on 300 mm wafers because the end product is not something you can make much of a profit from if you have defects that are common on denser nodes or extra costs relating to automating wafer transport. Sunk capex into those older machines and processes can't be amortized quickly enough if they switch to 300 mm.

[@soren6045]

The smallest technology node on 200mm is 90nm, maybe someone did also 65nm, but never 40nm or 28nm.

[@truegret7778]

Growing the ingots of single crystal silicon (Cz) is extremely difficult, and requires A LOT of energy. When I was at ARCO and Siemens Solar (early 1990s), we grew 35Kg that were 105-125mm diameter. As I recall this took about 48 hours. A full grown ingot was about 1.5m long. Slip dislocations were almost more common than not. For solar cell performance, if we suffered loss of structure, or slip dislocations, defects were seen as far as 1.5 diameters into the already grown ingot. During this period, we ushered in wire-saws to cut the wafers - less kerf loss. Up to that point, outer diameter saws were used. As I recall, we yielded about 1200 wafers per 1.5m ingot. Good review video. Thanks!

[@tulsatrash]

This is absolutely fascinating. Like you said it's amazing to see all these companies that are competitors all getting together to make a massive change in their whole industry happen time and again, a process that cycled until the turn of the millennium

[@krashd]

This sort of thing has always happened in computing, resolution standards from the early days of CGA and EGA up to the modern HD and 4K are decided by VESA, which is a co-operative body set up by screen manufacturers and GPU makers to make sure everyone is on the same page. Jpeg (.JPG) also came about because there were dozens of image formats in the 80's and the industry wanted to create a standard for them.

[@laernulienlaernulienlaernu8953]

Standardisation is the most rational approach to all manufacturing, however it sadly doesn't always happen.

[@RobBCactive]

The economic driver for greater wafer size hits diminishing returns, because chips grow capacity by increased transistor density rather than by physical area. The reticle limit will apparently decrease from 33mm to 26mm in planned future lithography, which will halve the maximum die area size. That shrink will increase the dies per wafer and reduce wastage on the outside, similar to a wafer size increase. Chip packaging is moving to multi-die assemblies at the high end.

[@soren6045]

Some corrections or more detail! 1st Defects in the wafers substrates are not always bad. Bulk Micro Defects are very important as contamination getter and for mechanical stability. So you have to prevent them near to the surface either by Epi-layer growth or Ar-anneal, but low BMD is also not always wanted. With CZ you cannot prevented it either. For power semiconductor, where you use also the bulk of the wafer for the device you need a different substrates made by the Floating Zone technique. 2nd FOUPs were not usual for 200mm. Either there are open cassettes or the cassettes are transported in so called SMIF pods. One important part of the 300mm transition was the integrated full automation. Automated loading, transport and dispatching were the standard from the beginning. 3rd The 1st 300mm FAB was by Infineon/Siemens in Dresden Germany for DRAM. The FAB was later part of Qimonda and is now back to Infineon producing the 1st power semiconductors on 300mm. The 1st mover to 300mm were Memory Fabs and not Intel. Logic Fabs followed later. 4th You get more than 2.25 yielding dies from a 300mm than from a 200mm. The larger the die the higher the cut off loss at the wafer edge. So a larger wafer is more area efficient.

[@GigsTaggart]

Was workers hurting themselves carrying 9kg around also accurate? Because that's not that much weight. Plenty of jobs require carrying more than that weight as a basic requirement. Usually more like 20kg in a manufacturing job is a bare minimum written into job requirements.

[@soren6045]

This will be an issue for 450mm, but for 300mm it was not.

[@chopper3lw]

Jon, I truly enjoy your briefings. They are so well done and quickly cover issues that I'm curious about but don't want to spend days researching. Thanks!

[@CapriMikeC]

I work for a company that manufactures some of the tools (chambers, reactors, etc). We made a lot of prototype 450mm stuff but so far, none has gone to production. Instead, we're making more of the 300mm tools and a handful of 200mm tools.

[@EnlightenedSavage]

Which company...asking for a friend.

[@Chiramisudo]

About 20 years ago before I started my career as a Software Engineer, I was a temp for a week at (I think it was) Sumitomo Mitsubishi Silicon Corp (SUMCO) in Salem, Oregon where they grew the 200mm ingots and helped maintain the clean room for those few short days. It was by far the coolest thing I'd ever done up to that point in my life. It used to be the major manufacturer in town, and one of the biggest chip makers in the US because it met the same tragic end as the rest of our chip makers. A catastrophic national security mistake that has bitten us more than once. We need to bring those jobs back.

[@markus4925]

I worked in crystal manufacturing. I saw a lot broken necks. This mostly happens when the finished crystal is ready to put out of the oven. In fact it happens while it gets put out. The crystal swings out of the oven. And the shear force does its job. Then you have to clean the whole machine because parts of the crystal fall in 1000 pieces. Which sometimes damage the glas crucible. Which isn’t so bad. It’s not reusable anyway. But the oven itself can get damaged. If everything works, the neck will be cut by pliers.

[@markus4925]

If there are any questions. Maybe I can answer them. I did the 300mm crystals for the most part.

[@davidb6576]

@@markus4925 Interesting that you were part of actual boule growth. Did you do any further work, like slicing and polishing, or were those all automated? And were defective boules broken up to be fresh melt?

[@christopheroverbeck3662]

@@markus4925 Do you think lower gravity would make the neck strength issue less pressing? I imagine you want at least a little to keep the molten liquid in place, but it shouldn't affect the properties of the formed crystal I think?

[@markus4925]

@@davidb6576 I could tell you what happens before the crystal is made. A worker had to settle down rocks of material in the crucible by hand. Piece by piece. In a stricter clean room than the actual growth process. The crystals itself have 3 marks lengthwise which grow together with the round structure. You use them to control if the crystal structure is still intact. That’s important while growing. You break up the oven process if you discover failed outer lines on the crystal. The next process was sawing. That’s true. I don’t have much insights there. But I visited the stage where the wafers are getting packed for the costumers. These are clean rooms of the highest levels. Like you see in Global Foundry videos for example. Yes. You can restart a process. Usually you do it if a crystal breaks up in the middle of the growing process. The crystal can break while in production by neck or at the position the crystal touches the surface of the melt. If the neck itself breaks you need to install a new neck by hand. After 3 failed restarts the whole load is considered as waste. You need to clean the oven and use a new glas crucible.

[@markus4925]

@@christopheroverbeck3662 The modern types of 300mm oven have superconducting magnets around. The magnetic field ist incredibly strong. Which makes accidents even more costly. A method would be a better gripping device which can hold the crystal within the machine as soon as the process stops. Less gravity. 🤔 How would you do that? Consider that the ovens are hughe. We talk about 4-6 floors in heigh. And 20 or so in one room. There is the holding device for a crystal. onlinelibrary.wiley.com/cms/asset/6165d38f-e38e-4296-a0c8-bb57a2bbf89a/mfig005.gif And there is an oven: assets.new.siemens.com/siemens/assets/api/uuid:062a0bfc66bc25fb30b8b53d2b0dc1f9914be300/width:1125/crop:0:0,021:1:0,96/quality:high/ekz3500-017-cmyk-v1-1.jpg What they don’t show it’s was underneath and above. This is separated from the floor the crystal gets produced. Through the round glass underneath the logo and the second one slightly below you can watch the (seed) crystal growing. Now you can imagine the size compared to a human, too.

[@mdl17576]

I worked with a guy who started in the industry when wafers were the size of a half dollar. He kept one and showed it to me one time. I had the chance to handle a few 450mm wafers back when the industry was still actively trying to make that move.

[@klobiforpresident2254]

I assume he carried one of the old wafers but I'd be no less surprised if someone pulled out a half-dollar coin. Been a while since I last saw them.

[@金小芬-k3r]

2 inches, /, prime grade, 280um, >20000 ohm-cm, SSP, 6.00 USD/WAFER, MOQ 200 PCS. www.weisswafer.cn [e-mail]

[@jaredlodico]

I have a phd in physics and have been working in nano tech for a long time. Your videos are pretty unbelievable dude, please keep them going! You should have your own show on discovery or something.

[@ddegn]

We often use the moon landings as an example of what humans can do when sufficiently motivated and financed. The tech used to make computer chips makes all the Apollo stuff look simple.

[@meeponinthbit3466]

Right? Getting to the moon is basically a big ass controlled bomb with some life support strapped on top. Semiconductor fab is where science becomes truly magic to all but a tiny few. LEDs are literally crystals that glow. A smartphone is a tiny glass object that can show you an unlimited number of cats, doing all the cutest thing.

[@gnualmafuerte]

@@meeponinthbit3466 Dunning-Kruger effect. You only think it's that simple because you don't know enough about it. A rocket engine is far from a "controlled bomb". It's an incredibly complex piece of machinery, that needs to operate literally outside of what we thought possible with any known material. Rocket engines don't sound so complex, until you remember inside the combustion chamber you'see temperatures of 3500C, higher than *any* metal melting point. And you're gonna have to be handling oxygen hot gas, which wants to react with EVERYTHING. It will literally eat your engine. And on the same machine, you have cryogenic propellants. One part of your machine is at 3500C, the other is at -180C. From cryogenically cold to tungsten-melting hot. All at hundreds of atmospheres of pressure. It is a LOT harder than you think it is. The principle is simple, making it happen is not.

[@ddegn]

Anyone interested in Apollo tech should follow the channel *CuriousMarc.* Another good channel for rocket tech is *Everyday Astronaut.* Everyday Astronaut has a lot of great videos explaining various rocket types. *Scott Manley* is another fun rocket related channel.

[@baptistedelplanque8859]

So in which of the two categories do you put the chips used in the Apollo program?

[@meeponinthbit3466]

@@baptistedelplanque8859 those chips were hella basic. There's a guy I saw doing that level of fab in his garage.

[@Queerthulhu0]

Thanks for this trip down memory lane. I worked in the industry at a metrology equipment manufacturer from 1996 to 2005. We started with (100,150) 200mm equipment with manually loaded cassettes and by the end we were handling 300mm FOUPs and supporting SECS/GEM automation standards. It was a fun time, I got to travel.

[@Mordecrox]

I like how the content is clear, concise and technical, and all voiced out, so you can get informed while keeping it as background noise or listening with your phone on the pocket, but I LOVE that if you decide to watch, you get those nuggets such as "look at this chonk" or "absolute unit".

[@grizwoldphantasia5005]

Got some questions from ignorance: * How thick are the saws which cut individual wafers off the cylinder? Or to put it another way, how much of the cylinder is lost in dust from the saw? What do they do with this sawdust? * Are there alternatives to mechanical saws? Say ... lasers, with or without sharks? * Could vapor deposition be used to grow individual wafers instead of entire cylinders and avoid the sawing process altogether?

[@B11video]

Wafers are sliced from the Crystal using diamond wire band saw blades, very similar to the process used to slice counter top slabs from a block of marble or granite, just in miniature. Water is used in large volumes as a coolant and lubricant. It also carries away the dust to a containment tank where the slurry settles out of the water. Ideally the water and slurry would be filtered , dried and recycled back into the process. Unfortunately this is expensive and very time consuming and since profit is the end goal, it's easier and cheaper just to use fresh water and dry raw materials. This results in large slurry retention ponds either on the surface or underground and ultimately slurry will leach back into the rivers lakes and streams. Yes lasers and plasma cutting are both options, however, heat creates it's own new set of issues in the process. Vapor deposition is incredibly slow and at this point not yet a viable option. This may change in the future. For now, seeding crystals is the most reliable option.

[@fatmouth007]

Wafers are polished after getting sawed, so all that dust probably gets removed then. You can't use a laser for this process because of the thickness. It's too thick to simply ablate (vaporize) material away with a high power laser, so you would be introducing a lot of heat to the silicon crystal. You can only realistically use lasers for dicing dies off of an already processed wafer, where the wafer is already fairly thin and easy to ablate without introducing extra heat.

[@grizwoldphantasia5005]

@@fatmouth007 Thanks. The sharks probably wouldn't survive in the ultra pure water, and lasers wouldn't be much fun without them :)

[@normantor]

Thank you so much!!! I worked at IBM East Fishkill from 2001 to 2008. I have so many memories. That is why we needed to go to Automation to move the FOUPS around. I was in the Automation Department. They were so heavy.

[@minhduong1484]

One of the major problems I remember with 450mm is wafer curvature. When slicing the ingot into wafers there is some curvature on the surface of the water. The larger the diameter the larger the curvature. Compounding this problem is smaller and smaller lithography feature sizes so even if 450mm had the same curvature as 300mm it would cause problems in lithography. One way to remove the curvature is to polish the water down which unfortunately adds to the thickness. All these increase the processing losses and the cost. I do not know if anyone in the industry has ways to overcome the increased costs to justify the move to 450mm.

[@andyargentina7056]

Your channel sparked my interest into the semiconductor industry a couple of months ago, and in a few weeks, I‘ll start working for an EUV technology supplier! Thank you so much for your work.

[@mitlanderson]

Dang, how did you find your job there?

[@savonwarrior]

May I ask which company supports this aspect of the EUV process?

[@andyargentina7056]

@@savonwarrior In my case, Trump in Germany :)

[@Rmx2011]

Wow, I think 300mm wafers are here to stay for a long time after what I just heard. Genuinely interesting topic and well presented, thank you!

[@Inquisitrr]

My uncle works for the Intel plant in AZ. He repairs some of the machines in the fab. Easily the smartest person I know. Super cool to get more insight on what he actually does! Thanks for sharing.

[@silverc4s146]

Excellent video Jon. I spent my entire career in semiconductor industry, from 1966 to around 2005. One area you left out of this remarkable treatise is the really antagonistic relationship between semi makers and their customers. Once a fab is completed and in operation, it has a finite lifetime, for the reasons you cover in this size progression. The only way to be profitable is to load the fab 24/7/365 with wafer starts for this lifetime. The end customers, cancel, reschedule, under forecast, over forecast, demand price concessions, and all manner of other unprofessional activities - because they know the fab has to run wafers or die. Each wafer is end user specific once started in many cases. Only commodity memory and some common logic devices and microprocessors are more flexible. After 40 years, I hated most of our customers…

[@arthurcuesta6041]

Nowadays I guess it's the other way around, since TSMC can pretty much choose which costumer to attend. Thanks for sharing.

[@ryandick9649]

You would really have enjoyed the relationship between the Motorola Semiconductor Product Sector and the other six sectors who bought the lion's share of the chips. They didn't call it the Warring Tribes for nothing, and the aroma of internecine conflict was ever-present.

[@rayoflight62]

Excellent video. In few minutes you explained the story of a lifetime in the wafer industry: The only thing better than "perfect", is "standardised"...

[@johnmitchell4616]

Thanks!

[@ksmith3062]

Great video. Filled in several gaps for me re: the history of silicon wafers. I work in the semiconductor industry for a major manufacturer and while building new 300 mm fabs, we have several 200 and a few 100 mm fabs in operation.

[@ksrcmurthy3484]

Thank you for the elegant, simple video without missing nische points. Thank you

[@timthompson468]

When I started in the industry in 1984, I was working on diffusion and LPCVD furnaces with 4” (100mm) wafers. My last field service job in 1992 was working on Scanning Electron Microscopes for CD measurement with 6” (150mm) wafers. That was about the time the industry started transitioning to 8” (200mm) wafers. The SEM had a stage that tilted to 45deg. This required a relatively huge vacuum chamber for the “specimen”. I had left the company by then, but I think the transistor to 200mm wafers prevented them from going further with their SEM CD measurement tools. I moved on to an R&D job working on a laser microscope that could handle 200mm wafers, but I had left the industry entirely before the 300mm wafers came out. I wonder what the cost of redesigning all the semiconductor equipment was at that point. It must have been huge considering a basic fab was over $1 billion by that time. It always amazed me how much money went into a typical fab, even in the 1990s. It’s mind boggling.

[@boydnelson2280]

Great Video, thank you. It makes me thankful that I mainly work with smaller wafers 150mm & 200mm, the pictures of the 450mm looks unreal.

[@nickj2508]

Very good and accurate video. 👍👍 Note 450mm was attempted 2 times. It stopped for the 2nd time in ~2014. The "obsolete" 200mm equipment has to do with controls and software, not the process. A lot of those 200mm machines are running on really old computers windows 3.1/NT/95. It is a huge undertaking to migrate the software and computers to new operating systems. There is a substantial refurbishment business to keep those old machines alive. as long as the OEM does not release the source code, there is no chance to make new version on old platforms.

[@paulds65]

Very nice video! I worked on 450mm lithography equipment in 2013. Project was cancelled after a year and I do not think it is ever going to happen.

[@scowell]

We had to give up rehabbing 200mm equipment... the availability of tools went way down. They're still very popular... lots of folks running Centura/Endura/P5000s/Producers etc. AMAT had to start up an 8" line again... I forget which one.

[@nexusyang4832]

man...i always learn something new every time i watch one of your videos. after a while i don't even know which video i saw what information because they are all so good and just all meld together... like a melt... of wafers. :-)

[@AdityaChaudhary-oo7pr]

Amazing video Jon . Semiconductor industry is the heart of development in 20th and 21st century .

[@Jasx_501]

This is a trip. I hadn't even considered this kind of transition and development required for wafer growth. Not to mention the connection to Moore's Law. Super cool.

[@joshuarichardson6529]

I used to work in super-flat wafer production. They had to have a flatness of 3 microns or less. That was so flat your fingerprint could throw it off.

[@napalmninja45]

I work as a maintenance tech in one of older facilities that Sumco mangers are talking about and most of the tools are 20+ years old. We’ve occasionally had to get parts for some of our metro tools on eBay. There are some people making new 200mm tools, but not near enough. Some people are also making upgrade kits for legacy tools to help them keep up. The 200mm wafers of today are often much thicker and more complicated than they were 20-25 years ago, and it takes legacy tools a long time to produce them. I don’t anyone really expected there to be so much demand for 200mm after the switch to 300mm.

[@amandahugankiss4110]

Punks. In my day we pulled crystals by hand. The way God intended.

[@alexanderm2702]

This sets up an interesting game theory situation.... if a company really wanted 450 they'd have to make huge firm orders from suppliers to get them to tool up; but then after the suppliers have tooled up then they're free to sell to other companies, who get a free ride (or a relatively cheaper ride at least). Demand for chips is relatively price-insensitive, so it would make sense for the industry to get together and agree "let's just not". Antitrust laws prohibit those kinds of agreements, but the law can't force companies to get together and agree on standards. I wonder if some companies were trying that with the 725 vs 735 um controversy last time around. (I have absolutely no idea about chipmaking, but is there any reason to feel strongly about 725 vs 735?)

[@johndoh5182]

I don't see it happening. Because of the node shrinks the amount of die that can come from a single wafer is in the many hundreds to thousands and the bigger problem is being able to cut a die ever smaller. You get into issues like how fine can the line be between two different die. So when these are the problems, somehow I just don't see the desire for all these fabs to go through the cost of retooling again. The cost would probably be 50 - 75 billion this time around because there's a lot more fabs. They made the move to 300mm when the industry was using a 100nm process node. We're about to be at a 2nm node (3 is in development, getting near risk production), and we're going to be at phases of 1nm by the end of the decade. 3nm is a density of 300 million transistors/sq. mm. Once below 2nm, which is 20 angstroms, the industry will change over to angstroms as the measure. But here is the problem, if you can etch 800 million to 1 billion transistors on a sq. mm, why in the WORLD would the industry want to have larger wafers. You're now in the thousands of die/wafer. This is a comment based on a question I asked about how small can a single die be: "Fully functional chips can be well under 1mm squared. They are typically fabricated on older lithography equipment using smaller wafers, however it is possible to fab 1000s of chips on a 300mm wafer. It is more cost effective and a better return on investment to fab larger more valuable ~20mm square devices on a large wafer." And there lies the problem. It's more cost effective to fab larger die on a large wafer, but with node shrinks getting you near 1 billion transistors sq/mm, the problem becomes cutting hundreds of vertical and horizontal lines to separate die. So, I don't see the industry wanting to make that even harder by having a larger wafer. Die is getting smaller every year. And then as said in the video, it's not like what you said in this statement " if a company really wanted 450 they'd have to make huge firm orders from suppliers to get them to tool up" No. To make die relies on making wafers which relies on a CRAP TON of equipment, so a single company wanting to tool to 450mm isn't going to get anyone to tool anything for that company. If Intel, TSMC, Samsung, etc.... said they wanted to move to a 450mm wafer, since those are the biggest players, the first step is convincing ASML to produce lithography equipment that can deal with such a large wafer, and frankly that would probably be a year debate right there, and then probably 8 - 10 years before they actually produced it. And that's the first step, KNOWING you can actually produce a die on 450nm. Then there's probably the other 50 companies that would be involved in making the REST of the equipment. THIS is why there's a consortium to deal with this. In fact if anything I could see moving these really advanced nodes BACK to 200nm because once set up, the faster speed of operation added with much smaller die so there are still many hundreds to thousands of die coming off a single wafer, that could probably bring prices down. As was pointed out in the video, it takes longer to work with and produce larger wafers.

[@johndoh5182]

@@aphenioxPDWtechnology No not true at all. The movement to the most advanced nodes follows a pattern. HPC (High Performance Compute) is always moving to the advanced nodes first. In the case of Intel, Intel moves onto their own advanced nodes, but it's available to other customers. In the case of TSMC, Apple is always their risk partner (first customer on a new node that has just moved into mass production, along with usually 2 other companies). In the case of Samsung, they move to their advanced nodes first with their small devices, but Samsung specializes in LP (low power) nodes. Try searching for TSMC customers percentage wafers or similar searches and you'll find pie charts and other charts that give breakdowns of who buys what from TSMC. Anyway, after TSMC has proven a node, THEN AMD, Nvidia and many other customers will move onto that node, so in the case of TSMC, Apple moved onto TSMC N5 last year with their small devices and the M1 processor. This year, for which products are about to start releasing, AMD and Nvidia will be using it. Intel launched a new line of GPUs, a first for Intel, with Xe graphics and first gen is named ARC. THAT is on TSMC's advanced node. But AMD and Nvidia is in mass production right NOW for AMD's Zen4 line of CPUs/APUs for desktop/laptop/WS/Server along with future console releases on TSMC N5, and AMD is releasing their new line of GPUs on TSMC N5. These products are here starting next month for the CPUs and probably the end of the year for GPUs. Nvidia has delayed their release of Lovelace GPUs but they should still be out by the end of the year, also on TSMC N5. Apple was SUPPOSED to move to TSMC N3 for their next gen products but that node is delayed, so they'll probably be on N4 and an advanced node of N5, whatever the designation will be. Samsung has already released on their 4nm. Intel will launch their 14th gen CPUs on their Intel 4. Now, these are the big names that most people recognize. Qualcomm and a few other companies are also customers of the two most advanced nodes out. Huawei is another one. So, HPC and small devices dominate the most advanced nodes, and HPC is HUGE. The world of servers is getting to millions of CPU purchases a year and is still growing, and they swap out equipment all the time. After those most advanced nodes then you get into other electronics that needs to be on small die and use little power, other than what Apple, Samsung, AMD and Intel make. You have other ARM processors that different companies make, but even part of those are on the most advanced nodes even after what Apple, Qualcomm and Samsung produce. Sure, an IC that runs a vehicle's emissions along with gas flow, air flow, etc.... to get the best performance/fuel efficiency are on lesser nodes and there's tons of trivial electronics that use less nodes. A lot of military equipment uses lesser nodes. But a node hasn't come out in probably 1.5 decades where it wasn't already booked up for 1.5 to 2 years. And also, if a company doesn't get good yield from their advanced nodes, it cuts into their profit, so you better BELIEVE they do everything they can to get yield up as quickly as possible. If TSMC for instance has a bad yield on N3, NO ONE will move to it. All that is worked out in contract. They have to guarantee a certain defect rate. You can't be a company like Apple and 30% of your ICs fail. Intel is different because they are a chipmaker and semi-conductor company, and this has been part of THEIR failure and why they've slipped in market share for both sectors of their business. So yes THEY have had issues with their advanced nodes, but TSMC gets that worked out before they can release a node and both their N7 and N5 releases were VERY impressive and made their customers happy and coming back for more, and caused Nvidia to move off of Samsung back to TSMC. So, if you get anything from this, there are multiple companies involved for fab. You can't make a blanket statement about failure rates. You can't make a blanket statement about ANYTHING. And there's a LIST of customers always waiting to be on the most advanced nodes, more so with small devices and HPC, where in HPC it give companies a competitive edge, so they will move onto those nodes after they're proven or even as risk customers. Maybe you should do some research before making a statement.

[@johndoh5182]

@@aphenioxPDWtechnology Dude you said that companies stopped jumping onto the next node when it comes out for a while. That's not true, at ALL, in any way shape or form. There is a WAITING order to get onto the more advanced nodes based on what you're making ICs for. HPC is ALWAYS on the more advanced nodes and it will never change. That's part of the competitive edge for a company. And if you didn't understand what I said it's because you don't understand the fine details of chipmaking/nodes/fabs, etc.... I have followed this industry my entire working life. I've followed the industry since the 80s when I was a computer tech in the military for 20 years and I had to learn the inner workings of a computer to be able to fix older computer systems, where you find failing logic gates and then replaced ICs that only had about 4 - 8 logic gates in an IC. I build systems and sell them and every day I follow tech news so I'm on top of what's going on in this business I've been following now for 4 decades. There see I can beat my chest too. And no, just because there is more features, cores, whatever going into newer CPUs, doesn't mean dies stay the same size or get bigger. This WAS the case, but NOW there is a heat problem because of transistor density. Cooling 1 billion transistors clocking at 5.5GHz over an area of 10 sq. mm on a 7nm power efficient node is easy. Cooling 1 billion transistors clocking at 5.5GHz over an area of 4 sq. mm on a 3nm power efficient node is harder, and when you get to 1 billion transistor on 1 sq. mm which is going to happen, well, that 1 sq. mm die with 1 billion transistors probably can't clock at 5.5GHz anymore. Power consumption would be too high, die glows red, blows up. The heat that USED to be spread out over 10 sq. mm is now all contained in 1 sq. mm. You do get power reductions per transistor with node shrinks, but that's not going to keep up with how much transistor density is increasing. So this is why die isn't getting larger anymore and companies are moving to MCM (multi-chip module). That AMD Ryzen desktop CPU is an SoC now, just like all modern CPUs are now. It's 3 chiplets to spread the heat. This problem gets worse with each node shrink. Yes, Intel and Nvidia increased some of their die sizes in the last gen, but they're on nodes which is at that borderline So you might be following the industry, but your failing to keep up with the reasons WHY companies are doing certain things, and in the world of HPC that's been moving away from larger die because of how much more heat is condensed into a much smaller space. So dies for HPC are going to be on a downward trend for size, not bigger. It's either that, or you have to compete against a company that's making faster products than you are. And this is why I used a bunch of words. Peace dude I'm done.

[@johndoh5182]

@@aphenioxPDWtechnology OK, I didn't quite read your comment correctly. Except you're still wrong. Apple doesn't just put the M1 processor, which is JUST finished about 1.5 years ago on the most advanced node that comes out of TSMC, they make their chips for SMALL devices on that MOST advanced node. It was only recently that Apple went back to making their own CPUs, but they've been a risk partner for TSMC for years. Samsung puts their chips on their MOST advanced node, for their SMALL devices. You're still wrong. Companies that compete in compute devices want a node advantage. It's not always about more transistors. It's also the fact that smaller transistors use less power and hence your BATTERY lasts longer. So that comment is still wrong. No, I didn't mean a company is making chips for toasters on an advanced node. Do research.

[@bobo-cc1xw]

@@johndoh5182 just adding to the your wrong hype train, as another internet expert. Newer nodes make sense yes but costs are going exponential. There will always be a person will to pay extra for extra performance and they sound like big names. But there are loads of applications that don't need it. If i read car magazines i would think there is loads of high performance stuff out there but most of the market is cheap and simple econoboxes.

[@phil2768]

I find the whole semiconductor manufacturing along with computer science and its whole history to be fascinating and shows real human ingenuity. Most lay people are only exposed to such practices and the histories through video's like this - KZbin is an amazing resource for learning new things. Thank you!

[@maxmusterman6030]

Danke!

[@Joshtk94]

I work at a 200mm fab and we are cranking out as many wafers as we can manage

[@chenzinc]

Another fantastic video. Working in Singapore's semiconductor industry, the smaller companies are still unable to transit out of the 200mm production process due to costs, while the big ones: GF, SSMC, Micron keep expanding 300mm fab space. I don't see them moving to 450mm, the cost would be absolutely insane.

[@alamagordoingordo3047]

Very good video, so explanatory, technical in the right amount. Thank you.

[@cjjuszczak]

Excellen video as always, i remember the move to 300mm and it was a great leap, and only later would we realise how it may be the last, kind of similar to how DVD, evolved to Blu Ray, but there may not be another disc after that :)

[@AbdennacerAyeb]

You are the man who touch extremely difficult subject in a very organized, well described manner.

[@christopherd.winnan8701]

Your best video yet. Not as technically baffling as a lot of your other stuff.

[@OnlyUseMezBladz]

id love to see a similar video on the 450mm transition that Intel tried to push

[@experienceaeiou]

this video goes *hard* I have been curious about semiconductor fabrication for years, this was such a cool peek into the industry

[@patbrown5168]

Great video. Not many lay people know the complexity behind IC fabrication. Thank you for the wonderful video (retired HP/Agilent/Keysight test equipment engineer)

[@Yezpahr]

1:29 Wow, that one has a load of empty squares while some others have inherently faulty chips that aren't even complete due to being on an edge... It never ceases to amaze me that they aren't just skipping those areas in the edges but this one apparently was made to skip a loooot more.

[@charleschapman2428]

I was growing these crystals back in 1974 in north east NJ, I think the company was called National Semiconductors. I really loved that job but unfortunately they closed up shop and moved out west somewhere.

[@Nivola1953]

One of the main reasons to increase wafer size is Electrical Yield, that is the % of good dice on a wafer. That depends on many things, but for sure the dice close the edge are going to suffer from more yield loss, if nothing else because you’re trying to square (dice) the circle(wafers). As the diameter grows the ratio of the perimeter (2pi*r) vs the area (pi*r^2) reduces, hence yield increases.

[@pauloalvesdesouza7911]

Excellent video. Shows an aspect of the industry I had no idea of. The numbers are mind boggling.

[@PetsoKamagaya]

They are usually called ingots, not crystals, although it is one huge crystal growth. But as usual, you have done a superb job in digging up the history of semiconductors. Bravo!!! p.s. I was at Entegris when Intel, TSMC and Samsung got together and tried to drive the transition to 450mm. In terms of lithography and mechanical interfaces, I think it can be done. What I heard was that the silicon growers could not sustain volume production of the 450mm ingots (they were huge) because the crucibles just didn't last long enough. I have heard that from a Momentive employee that even for 300mm ingots, the crucibles have to be replaced every 3 or 4 days.

[@kennethtan6403]

Thank you and much Love from the Philippines.

[@renardrougesombre]

If I had to make a guess, I do believe we will rather see epitactic processes to produce wafers in the future. No matter what type but while we're making progress in materials research there will be a breakthrough. Again a stunning insight into this part of semiconductor industry history. gj

[@AmanSingh-nw7lw]

I have seen Molecular Beam Epitaxy in the lab of my department, its beautiful

[@Blubb5000]

Moving machines from 9ft space requirement to 6ft is not a *3%* space reduction I think you meant *3ft* space reduction.

[@codymitchell4476]

Proud to work at the First analog 300 mm wafer fab in the world! Texas Instruments FTW

[@sagetmaster4]

A week ago I wouldn't have thought this video would be interesting. Today I saw it and got so hyped to watch

[@robertpearson8546]

The first low-orbit fab will probably use 2m wafers. In 1979 when I was working for TI I told them to invest in a low-orbit fab. Ship up a pound of silicon for $10,000 and ship down $50,000,000 in ICs. Crystals grown in microgravity have a lower defect rate than those grown on Earth. When pulling crystals in microgravity, weight is not an issue. To fabricate ICs you need two things - vacuum and intense, clean heat. In orbit, for vacuum, just step outside. There is no need for large enclosures to resist air pressure. You can increase the separation between the wafer and the diffusion source, reducing spherical aberration on the ICs. For clean heat, use a mirror.

[@agenericaccount3935]

It's really neat to think about all these great minds seeking every possible efficiency in every corner and managing to do it so well.

[@buckadillafilms]

Thank you for shedding light on such an interesting topic. I'm not sure how popular this video will be either, but I won't forget it anytime soon. Great work.

[@janami-dharmam]

the small size wafers are widely used for R&D in many university and research labs. 50 years back I used to wonder how a small seed can hold several hundred kgs of a Silicon crystal at a high temp. I still wonder.

[@JonMartinYXD]

Silicon Edge (a UK company) has a cool little die per wafer estimator tool on their website you can use to see how die and wafer sizes affect potential maximum yields. It is linked right off their front page. They have wafer sizes going back to 51 mm and up to the not yet existing 450 mm behemoth.

[@kcgunesq]

Size is an advantage, until it isn't. This is true in semi-truck trailers, cargo ships and apparently, silicon wafers.

[@justinhamill1931]

Great video! Thanks for making it I enjoyed every second of it

[@jedibusiness789]

You missed one other variable in the delay between 200 to 300mm. Improvement in thinner line photolithography allowed more chips on 200mm. That development stopped two manufacturing sites for 300mm

[@cnordegren]

Absolutely great video! This transition has been a real headeache for the industry. The lesser the circumference curvature the highe yield.

[@Raptorman0909]

When I last worked in the industry in the automation side we began testing overhead vehicles capable of 450mm wafers -- that was 2012/2013. I suspect that we may stick to 300mm for a long time as there are tradeoffs between a larger wafer which might be cheaper per die but only if the uniformity across the wafer was adequate and larger wafers will be more difficult to achieve that. Just as the CPU/GPU makers are going to chiplets to get the size needed by using more than one chip as a way to limit the defect rate it may well be the case that 450mm will just not reach the defect rates that 300mm have. Lastly, controlling for temperature changes, which as critical for litho, is harder with larger wafers and even harder as feature sizes get smaller.

[@ntabile]

I saw one fab transitioned from 200mm to 300mm wafers. That company is TECH Singapore and bought by Micron where the transition happens.

[@avejst]

Great walkthrough of the process. Thanks for sharing your passion with all of us 🙂

[@erikbarsingerhorn4485]

Absolutely fascinating to see how this industry works. Eyes on ASML....

[@laurenceharris8160]

The increase in diameter buys only just so much. Trace width gives just so much. Simplicity might win out over all the rest and might make fabrication easier at smaller chip sizes. Manufacturing equipment can be bought

[@geneballay9590]

as usual, another very informative, timely and well presented video. thank you for all the work, and sharing.

[@davidprice875]

Another example where competing companies cooperated on massive change is in mobile telephony with the rapid convergence around digital standards. This included the US moving from ANSI-41 to a GSM based system. A lot of the impetus came from customers and likely handset manufacturers once smartphones came to dominate

[@taylorjohnson4943]

I've been watching your videos and they're really good. You've really taken the time to be very thorough with your presentations I enjoy them. Thanks 👍

[@blueguy5588]

Great info. Please consider a video on IC layout if you don't have one already.

[@Redsson56]

Technology companies working together to set important standards has been a well established practice for many many decades.

[@TakeiRyo]

Would you consider doing a video on 450mm wafer transition? I know they developed SEMI standards for 450mm and suppliers did research and development of 450mm... but fell short. I'd love to know the history there as well

[@alexlefevre3555]

A fascinating look at another very complicated cog in a hugely complicated manufacturing process. The semiconductor industry is about as akin to magic as we get as a species. Also blows my mind to conceptualize wafer scale devices on a 450mm behemoth...

[@SF-fb6lv]

This is such a good channel; thank you for all your research, insight, and rich content.

[@DoctorWhom]

11:48 just FYI youtube puts subtitles at the bottom, so if you caption a picture there, it just gets covered, and I have to pause the video to read.

[@NovaValentis]

I worked at Siltronic during that time. The 450mm Wafers were such a challenge. I still wouldn't know how to handle those things with robots reliably without them breaking due to warping, air resistance, inertia. If you need any details of that time, feel free to hit me up.

[@NovaValentis]

@+①⑨④⑨⑦③⑨⑤④④⓪Whatsapp lol totally not suspect! :D

[@exidy-yt]

This is just completely and totally fascinating. I never paid any attention to the other side of chip fabrication, and your video on "The Amazing, Humble Silicon Wafer" is next in the queue for me. I wonder, with all those 150nm machines being 'obsolete' now, I wonder if it would be possible to buy these machines up on the (relative) cheap and become a source of low-end but still often needed CPUs? I am sure there's a ton of factors I'm not considering, but I do wonder if there'se money to be made here....

[@davidwilkie9551]

Thoroughly Modern Magics and/or Super Sciencing Careers. This and the Fab Machines are mind boggling technology.

[@Sonic_Shroom]

Can you please do a video about the sawing process. Of wafers and crystals.

[@Indrid__Cold]

As a student of crystalography, the Czochralski method is the best compromise between flame fusion (used to create TONS of synthetic sapphire for cheap jewelry l like class rings) and the flux method, which grows the internally and externally purest crystals (but takes a year or so).

[@spladam3845]

Great video, I'm so glad someone is making this content as this information is not as easy to come by as most tech history is, thanks for the research and work.

[@RahulYadav-nk6wp]

That is some gold content, sire.

[@legiran9564]

Highly interesting. Will you also do a vid about the challenges of 450mm wafers?

[@wuliqunyy]

As always. This is great video! Thanks, keep it up!

[@KallePihlajasaari]

I remember reading that the size of the main plumbing to supply deionized clean water to the fabs was about the same size as the wafers. So to get a 300mm fab running you need to have a massive water purification system that is secure from power failures and earthquakes and what not.

[@rich_in_paradise]

Something glossed over in this video is the reason for larger wafers. Some benefit comes from getting more dies on a wafer which reduces the time spent transitioning wafers in/out of different machines in the process. But mostly it's about increasing the die size. The larger the die size for a given wafer diameter, the more space is wasted around the edges of the wafer. To keep up with the so-called Moore's Law dies got bigger over time as well as feature size shrinking. I think the reason why the industry isn't pushing for larger wafers again is that we're moving to 'chiplet' designs for the most demanding products now, e.g. AMD's Ryzen and Threadripper CPUs. Or maybe the lack of larger wafers is the reason to move to chiplets. Either way, with only the largest designs showing a benefit from larger wafers, it's difficult to justify the cost of another wafer size upgrade.

[@SianaGearz]

Consider that as you're pushing the process ever further towards higher transistor density, defect density increases. A very large chip today is maybe 3cm across, that's some vaguely 60-ish dies for the 30cm wafer. What happens if you have just a dozen tiny little defects for that wafer? Your yield is suffering, you could be throwing away a fifth of your product. Now imagine if you had some gargantuan level chips that are even larger than that, your count of defect free dies will be decimated somewhat fierce even further! So you can't increase transistor density and also increase die size any further, you get to choose one or the other. You want to make transistors smaller to decrease their gate capacity, so that changing their state takes less energy every time. And the problem is making the wafer larger doesn't make the problem go away, the defect density per unit of area just isn't going to get better. So larger wafers would hypothetically save some cutoff waste on the periphery, but they wouldn't actually help you make large dies.

[@MrStevos]

Thanks for this, I know nothing of the business, but was thinking exactly the same thing

[@tomharger2573]

Loved the video. And if it hadn't been good, it was still worth the watch just to hear the word "FOUP"!

[@ricardokowalski1579]

Solid content 1- Is the wafer size a "Concorde" moment? The intersection of material limits, cost, and diminishing returns of scale is fascinating 2- The next big thing collides with "good enough" and produces interesting debri. If you are making cheap calculators, do you *really* need to make them in the largest available wafer?

[@Kynareth6]

Calculators certainly don't have chips from 300mm wafers.

[@ricardokowalski1579]

@@Kynareth6 I hope so. But the issue is that if the machinery for 200mm and smaller wafers becomes obsolete and unsupported, one day it may *have* to be cut from 300mm. Respectfully.

[@naughtiusmaximus830]

The only non metric measurement I prefer is Fahrenheit for room temperature. Celsius is too coarse and adding an extra digit is cumbersome. I like miles over kilometers too just because I’m used to it.

[@djnavari]

Fantastic technical research

[@xenuburger7924]

Fully automated molecular beam epitaxy of SiGe etc on 200mm wafers is kind of bleeding edge. I wouldn't say 200mm is an "old" size.

[@ekstrapolatoraproksymujacy412]

your pronunciation of "Czochralski" was almost perfect!

[@lawpickinglocksmith7689]

Very nicely explained! Thank you so much.