AXI Stream basics for beginners! A Stream FIFO example in Verilog.

[@FPGAsforBeginners]

Hi All, Thanks for checking out my video! A couple of notes: 1) I didn't go over the KEEP and STRB signals in this video. They're basically just fancy byte-wise enables. When we get into the bigger AXI interface video I'll explain them further. 2) Code in Github here: github.com/HDLForBeginners/Examples/tree/main/UART 3) Feedback form for your comments: forms.gle/ssNwzTKiioj3RNHD9 4) Timestamps in the description if you want to find something in particular. I'll include them here below too. Appreciate you all! Bye!! 0:00 Intro 0:35 Interface Overview 1:19 Ready Signal 1:57 Last Signal 2:16 Ready-Valid handshake rules 3:07 Code Explanation 5:35 Simulation Explanation 7:31 A wild bug appeared! 10:30 Full Axi 11:23 Outro

[@user-ww2lc1yo9c]

If one knows that the interface shall transfer fixed size packes e.g 64 words per packet, is the tlast still useful to use?

[@Mtron1000]

Stacey you are a gem, digital design isnt represented enough on the internet especially at this level of tutorial/instructions. Its all just opaque as hell documentation. Thank you for your service!

[@sebastiangallo4265]

OMG I ABSOLUTLY appreciate how you found a bug and immediatly put up to solve it live(ish). It's so much sothing seeing experienced people having mistakes too and solve them as they go. Such a great job!

[@abdulbary3668]

I asked chatGpt about good tutorials on Verilog, he recommended this Channel 😂. I love it. Keep it up 👍

[@dariocardajoli6831]

Aaaand mine was the 255th like . . 8 bits well deserved to say the least. Thank you very helpful stuff

[@shrutitajne]

Wonderful Stacey!! This is one of my favorite youtube channels and I don't get zoned out while learning. I am a beginner in this industry right now and your videos are so so so helpful! Please make further parts as soon as you can!

[@CapoXProductions]

Awesome content! Thanks Stacey!

[@mth469]

Thank you. Can't wait to get started on my journey.

[@MrDanimalicious]

Thank you so much for making these amazing videos! Would it be possible to also occasionally show a high-level block diagram of the architecture? I think it would be helpful in understanding where the different modules fit and how they connect to each other. Looking forward to the next one!

[@FPGAsforBeginners]

This is a great suggestion! After I made the video I realised it probably would be beneficial, especially for anything bigger than this. Will definitely include it next time.

[@magicflour]

I'm newly hired in an FPGA company and am still learning protocols. This is an excellent introduction to something quite simple but bogged down by its documentation. Thank you!

[@SkyRiderJavelin]

excellent content very useful, thank you for posting

[@electronash]

Excellent explanation. Thanks.

[@turgutyldrm816]

Thank you Stacey, it is a wonderful video. I look forward to more videos on AXI stream:)

[@georgeyu9898]

Looking forward to the next one!

[@Dom-bo8wd]

Thanks so much Stacey!

[@user-wm1bo5eh5t]

amazing~ thanks

[@tryssss]

very nice job :) thanks

[@wel97459]

Awesome video!

[@RandomHubbb]

Hey Stacey, thank you for the amazing video! Do you have a code where you pack/unpack data from axi bus? Also, i could not see the fifo code in github, it is some. xci file that does not show the verilog code....

[@ganauvm270]

amazing

[@wisnueepis3593]

really?? I think that only male work with fpga, you are great lucy! good job!

[@user-vz4zx5hk3o]

nice

[@ayazar]

Hi Stacey, thanks for pushing good contents to KZbin! If I understood correctly, around 9:40 you mentioned about a time out for "not driving ready" and said that slave must become ready at some point. Actually, I have never heard about a limit on ready, AFAIK the slave can keep ready indefinitely. I did a quick check on AXI Reference Guide from Xilinx and other resources and didn't find an information about a time out value. Do you have a reference for this or did I understand it wrong? Thank you!

[@FPGAsforBeginners]

Hi, thanks for your comment! You're absolutely correct. That was the point I was trying to make at 9:42, there isn't a time specified! :)

[@ayazar]

@@FPGAsforBeginners Sorry, my mistake. I listened again and you said there isn't a specified time but what I heard was "there is". Thanks for the response :)

[@varunsharma3860]

Hi Stacey, Thank you for you video! Can you please show how you made/generated(what parameters you selected when generating the XCI) AXI tx_fifo to stream data to UART? Not sure if you already have a video on this. It'd be a great help if you can do this please. Thanks! :)

[@FPGAsforBeginners]

I did make a video! Here ya go! kzbin.info/www/bejne/b5eXmmR8ppyrl80

[@varunsharma3860]

@@FPGAsforBeginners Thank you Stacey! I also filled out the google form and requested some video on JESD204B related topic. Any help would be appreciated!

[@Jonathan-ru9zl]

Hi! If i build custom IP, with signals bus compatible to full AXI4, and connect it to Zynq for example in Vivado, how can I configure the setting so I can use it in burst mode?

[@stark9397]

Hello Stacey . Interested in MIPI CSI-2 before?

[@meechil5163]

Hi, just curious which EDA/platform you are using for writing SV and generating waveform?

[@FPGAsforBeginners]

I used Vivado for this :)

[@yeganehaghamohammadibonab9292]

Why there's no "read response" signal?

[@FPGAsforBeginners]

This is AXI-Stream, which doesn't have a read response. The AXI and AXI-Lite interfaces use that signal.

[@yeganehaghamohammadibonab9292]

@@FPGAsforBeginners Got it! thanks!

[@RandomHubbb]

Where is the freaking fifo code? lol

[@amirmm5352]

Hi. tank u for you describing about some subject that is so rare to read, but can u please wear a normal make up . and again thanks for all your work u have done.

[@stark9397]

Hello Stacey . Interested in MIPI CSI-2 before?