Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)

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FPGAs for Beginners

Күн бұрын

Пікірлер: 58

@SergeyUstinovDih Жыл бұрын

The most clear and detailed explanation I've seen for a long time.

@FPGAsforBeginners Жыл бұрын

Glad it helped!

@felipeferreira1960 11 ай бұрын

Thank you for this class. What incredible and detailed teaching, besides being straight to the point. It's hard to find good content on this type of subject; I really hope you continue sharing this kind of knowledge that ends up helping many people. Hugs from Brazil.

@danclementi8454 6 ай бұрын

This material was presented as only someone who really understands what they are doing can. I was especially impressed at how Stacey anticipated virtually all of the questions I had. Great job!

@trevinvaughan5411 5 ай бұрын

Finally, a tutoral on Xilinix SoC's that makes sense.

@premc5564 11 ай бұрын

Really amazed to see how simple you made this topic for a beginner like me to understand. Thanks for the video. Looking forward to more such video tutorials!

@MohAli-j5u 17 күн бұрын

You are amazing Stacey. you delivered a very high and clear explanation. keep it up!

@brajitpaul5679 5 ай бұрын

I absolutely love how involved you are throughout. Amazing.

@ronalddejong4692 Ай бұрын

Thank you Stacey for this tutorial. You explained everything very well. Also graphically. Very impressive! Keep up the formidable work!

@mietto 5 күн бұрын

Lovely accent, makes it so much easier to listen to the presentation :)

@gauravtiwari605 8 ай бұрын

This is the first video in which I really understood what the teacher is teaching... Thank you... Awsm video...

@nmidu 11 ай бұрын

This is the channel what i need! Thanks for share this content. Greetings from Argentina

@BoneohSanitarium 4 ай бұрын

Excellent! Thank you, Stacey, great job. You're explanation of the processing of the 'how' and 'why' are super!

@matthewbucknall8350 Жыл бұрын

Okay, this is weird - I was looking at Zynq SoCs only a couple of hours ago for a future project. I've used Vivado a fair amount when working with Artix-7s but never Vitis, so I look forward to part 2. Thank-you for your video.

@elmiguel1969 3 ай бұрын

This is a top video. I have been struggling with my own design using Zynq and my own HLS IP created in Vitis. Vivado has been reporting I/O resource over-utilisation and problems with the placer during the Implementation run. Now I know that the key is to create the HDL wrapper first.

@nikolaykostishen6402 Жыл бұрын

Thanks for the nice video tutorial. Waiting for the next part.

@jawadbdour7481 3 ай бұрын

Thank you so much for the very useful tutorial, hope you keep on these tutorials and go further for advanced videos!

@ChuffingNorah Жыл бұрын

Excellent Vid & Explanation of this complicated Software & Project. Keep up the good work Stacey! 😁I've just bought a Zybo Z7-10 purely on the strentgh of this Vid!

@abdullahalnafisah5159 8 ай бұрын

Many thanks for your efforts Stacey. Your videos are very useful and we really appreciate your time.

@sammyiyi7136 8 ай бұрын

Stacey, you are a legend!

@clearlake2112 Жыл бұрын

Great to see your new post Katy.

@CSFitness1 Жыл бұрын

Great video, always liked Vivado more than Quartus, much easier to learn

@lontongtepungroti2777 4 ай бұрын

thank you for the amazing explanation:) love the enthusiasm

@richardgraham9134 Ай бұрын

Wonderful explanation!

@allfocuses Жыл бұрын

Thank you for the series. Could you please make a video on some applications such as connecting camera, servo, dc motors, some sensors and etc?

@ideajin20sh Жыл бұрын

very clear and easy to understand, thanks!

@markganus1085 6 ай бұрын

a stacey plus vivado. i like it

@Ajay-bk4xh 6 ай бұрын

Thank you, very helpful.

@floridaadventurediving144 3 ай бұрын

Great video thanks for taking the time.

@benq3605 Жыл бұрын

Thank you very much Stacey for this nice tutorial. I followed your 2 parts using Vivado 2023.2, but after using the exported XSA file in Vitis, there is no driver for block ram, I am able to use GPIO but the platform created has no driver for xbram. Either Vivado 2023.2 does not include it in the XSA file, or the Vitis software has a bug and can't see it in XSA file. I would like some advice on this

@giorgiop509 Жыл бұрын

Useful example, thank you

@Tiget2612 Жыл бұрын

Great video! I've been struggling a lot with programming FPGAs for my master thesis and your videos have by far been of the greatest help. One question about the peripherals: the way I understand the block diagram now is that the AXI interconnect is connected to both the LEDs and switches in this case, not the other way around. So, in this case, can the switches be used in this case to provide input back through the interconnect to the PS to make the LEDs turn on for example? Basically, is the master and slave AXI connection a two way street?

@FPGAsforBeginners Жыл бұрын

Yup, precisely! Actually in the Vitis video, I'll show how I connect the switches to the LEDs to do just that.

@kramer3d Жыл бұрын

The question you asked has 2 components… #1 as stacey replied to already… yes you can trigger interrupts on gpio input change to notify the zynq processor BUT YOU ALSO ASKED “is axi a two way street” which is an entirely different question… #2 Is axi a 2 way street? No… only the master can issue read write requests from peripherals!

@angelg3986 11 ай бұрын

I guess, those of us who don't have Zynq can use a microblaze for "processing system". I train on a board with a xcku15p-ffve1517. IMHO, the GPIO even doesn't need 4k range - 128 bytes looks sufficient. Are there considerations to put it bigger (like faster address decode, etc) ?

@ranjeetkumar2709 Жыл бұрын

great explanation. i am from india and i really enjoy your tutotial for block design but what we basically trying to do here ? turning on or off led through zunq processor or something else ?

@gogozxy5333 7 ай бұрын

Thank you for such a great video!

@asgarreza8602 2 ай бұрын

I am using ZCU104 board i have added the ip but not able to connect the reset to processor system reset as it is showing no matching connection found

@OpenGL4ever 4 күн бұрын

As I understand it now, I can use a Zynq board to load various finished softcores into the FGPA and then access them from the ARM CPU via various addresses. But I have a question about this. Is a Zynq board also suitable for improving skills in Verilog? Can I also just use the FPGA on the Zynq board without the ARM CPU, as is the case with classic FPGA boards, e.g. like the Spartan series boards?

@agpan7854 7 ай бұрын

When do we use Constraint files?

@Epithom 7 ай бұрын

Great video 👍👍👍

@haqnawaz4668 10 ай бұрын

Hi Stacey, can you please briefly explain the pin connection of FPGA board with laptop. I have USB blaster with JTAG. thanks

@مروانعبدالخالقذنون 4 ай бұрын

Dear teacher I have built a module using PL part only to calculate the summation of Bytes. Now, I try to use the Zynq with axi-gpio to read the final value of the summation. I test each circuit individually, it is works correctly. The problem is that when I connected them together (the PL with PS), I did not get any results by the Zynq at the serial monitor. Please, if you can help. Thanks.

@dulminedirisinghe5646 7 ай бұрын

well done!

@emwave100 3 ай бұрын

I have wanted to do an FPGA project for quite awhile now and haven´t gotten around to it. I wanted to create maybe a small 8-bit microcontroller with the alu and a large enough instruction set to be considered general purpose, with registers, and control, etc. There are several companies that offer fpga development boards, could you recommend one to me that would be sufficient to complete my goals? I would like to code in Verilog preferably but VHDL would be fine also.

@orzamarius3537 5 ай бұрын

You connect your peripherals to the interconnect_aresetn, when the Processor System Reset has a dedicated output called peripheral_aresetn. Is this going to be a problem? The instinct tells us that there are differences between these two resets generated by the reset IP. What can you tell us about that? Thanks!

@FPGAsforBeginners 5 ай бұрын

There is a slight delay, as far as I know, between the peripheral reset and the interconnect reset. So that the interconnects can come out of reset first. However, unless your peripheral specifically needs this reset timing, it doesn't really matter in practice which is connected.

@marwanal-yoonus280 4 ай бұрын

Dear teacher Please, I have a problem during reading the status of an output switch on Zybo Z7-10. I use Vitis to program the Zynq processor with Gpio connected to a slid switch. I make the switch (input2) status as a condition as shown in the program below if (D == 1) ; The following program works only when the input2 signal that was connected to Gpio IP starts from ("1") but the program does not work when input2 signal starts from ("0"). ////////// while (1) { D = XGpio_DiscreteRead(&input2, 1); // input2 from a slide switch if (D == 1) { sum_all = XGpio_DiscreteRead(&input, 1); // input is a 32-bit data printf("%x " , sum_all); sleep (1); } else { XGpio_DiscreteWrite(&output, 1, 0); // output is a LED printf("No_Signal "); sleep (1); } } ///////////// i.e. the program works only when I change input2 from "1" to "0" but does not work when the input2 start changes from "0" to "1".