BQ77915 BMS Schematic UPDATE!!! | BMS Design Series Part 06

In this video, we will update the schematic and layout for the BQ77915 BMS that will control the Milwaukee drill battery pack.
This new update for the battery management system will improve allot of the shortcomings of the original design.
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[@gsuberland]

Been using Altium for ages and didn't know about Ctrl+M for measure! That'll come in handy. Regarding the plane layer conversion, you do it in the stackup manager, but you have to turn off symmetric stackup or it'll make L2+L3 both planes. Another thing to watch out for is that Altium generates inverted Gerbers for plane layers, i.e. the Gerbers describe the voids in the plane rather than the copper, to reduce the file size. This is fine in 99% of cases but I've had JLCPCB's support folks (not the engineers) get confused about this and delay my boards while waiting for clarification. While watching this I remembered a cool trick I saw on an OCP blade chassis power distro board. They had several hundred amps coming in via a blade connector on the end of the board, passing through some filtering, then flowing down a long plane to a series of buck converters generating the 12V rails for the blades. I think it was 10 layers in total, and the layers ran in alternating PG pairs. I looked at the schematic and found something really odd: they had a set of current balancing ICs (something like LTC4355) that you'd normally see used in ideal diode-OR applications for multi-supply load balancing, except all of the FETs were connected to the same high-side rail and low-side rail, rather than balancing separate incoming supplies. So the power went from the blade, through a short plane to the filters, through another short plane to the load balancers, and finally out onto the long high-side plane for the buck converters. I puzzled about it for a few hours before I figured it out. They were using the current balancing ICs to evenly distribute the current density across the planes, preventing current density hotspots! Better yet, because the FETs are all balancing the exact same rail, the voltage delta between them ends up being really small so the forward drop is just a few mV, meaning the FETs are driven very close to full forward conduction and barely any power is lost. I ended up loading up Altium and building the same board design to test it out with the PDN Analyzer plugin, both with and without the FETs, and it made a huge difference in current density hotspots. Really clever trick.

[@eetengineer]

That is a pretty neat trick. Might be something to replicate for experimenting.

[@marv4895]

thanks for the video. be careful with the pin numbers of the jst. we often had the problem, that the vertical had the numbers mirrored in compare to the horizontal. which you only first realize when you want to plug the cable in and see that you'll have to switch all the cables around in the housing.

[@eetengineer]

Thanks for the tip

[@leigh7529]

Nice vid! Have you noticed any cell-balancing issues with this chip? I've been running a fleet of ~10 4-cell BMS boards for ~5 months, and they seem to become increasingly unbalanced with heavy usage, despite charging them 12+ hours each day. Maybe thats nornal for LiFEPO4...?