Bus Multiplexer Design | 30 days of VERILOG coding | Day 28

Learn Verilog with Practice : www.whyrd.in/s... Please give your feedback here: forms.gle/JHnE...
Day29: • Verilog codes from KMa...
Today's video resources:
HDLbits : hdlbits.01xz.n...
To personally connect with me, follow me on :
LinkedIn- / rajdeep-mazumder
Instagram- / rajdeep.jgd
________________________________________
Watch Next:
VLSI interview prep series: • VLSI interview prepara...
VLSI Podcast: • VLSI PODCAST
VLSIgayan: • VLSIgayan
Start a VLSI project: • VLSI Project That Will...
Verilog roadMap: • Learn VERILOG for VLSI...
#whyrd #vlsi #verilog
Disclaimer: The following video and its contents are presented for informational purposes only. The author of this video has made every effort to provide accurate and up-to-date information based on their best knowledge and research available at the time of recording. However, the author cannot guarantee the absolute accuracy, completeness, or timeliness of the information presented.
it is important to note that the views, opinions, and interpretations expressed in this video solely belong to the author and do not necessarily reflect the views of their employer or any other organization with which they may be affiliated.
Viewers are reminded to exercise their own critical thinking and judgment when consuming the information presented in this video. The author , shall not be held responsible for any losses, damages, or consequences arising from the use or misuse of the information contained herein.

[@rahulkumarsahni8765]

please do 9*1 mux, i didn't get the output

[@whyRD]

Oky will do today

[@shiamahamedluvon117]

module top_module( input [15:0] a, b, c, d, e, f, g, h, i, input [3:0] sel, output [15:0] out ); always @(*) begin case (sel) 0:out=a; 1:out=b; 2:out=c; 3:out=d; 4:out=e; 5:out=f; 6:out=g; 7:out=h; 8:out=i; default:out=16'hffff; endcase end endmodule

[@nissanbiswas8432]

Thanks you so much sir.

[@kpj4985]

Hey Hi please please Give me Gauidance ...I am Referring One book Verilog LRM in That Book I Can't Understand Chepter Number 15 ..... Please Suggest me Where I find Material Regarding Chepter no 15... Topic Name : "" Timing Checks using Stability Window"" And "Timing Checks and Clock Control " Example How To use $setup $Hold $skew $fullskew