Cascading Issues of Dynamic CMOS | Solution of Cascading Issues in Dynamic CMOS

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[@pokpikchan]

I really like the way you put up these animations. It helps me to understand easily.

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[@nogymworkout243]

These videos are pure GOLD 🥇

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[@alabamaroaster1086]

this is so good..only if college professors could teach this way! great work!

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[@ateebshivalli3618]

🎉🎉🎉🎉 Thank you sir For your great explanation

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[@trinath6941]

God for ECE, I dont know why i am paying 15 lakhs to my institute. you are teaching 100*Better than our proffesors

[@dwaipayanroy3232]

kiit ?

[@rahulwadhwa_0494]

Are u in 3rd yr now

[@rahulwadhwa_0494]

Which college

[@trinath6941]

@@rahulwadhwa_0494 vit Chennai, but anyway that comment was 2 years ago...now I'm passed out 😂

[@8L4CK_P4NTH3R]

​@@trinath6941 how are the placements in vit Chennai, did you get placed or are you doing masters?

[@Golukumar-vj6kk]

great explanation.....thank you.

[@EngineeringFunda]

Your Appreciations, care and share matters a lot to me. #EnginneringLove. All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏

[@yousefmasarwe6332]

Ily your the best❤❤❤❤❤

[@EngineeringFunda]

Your Appreciations, care and share matters a lot to me. #EnginneringLove. All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏

[@UECAshutoshKumar]

Thank you sir 😊

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Your Appreciations, care and share matters a lot to me. #EnginneringLove. All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏

[@rakshitadadhich7879]

Thank you for sharing your gift of teaching with us sir u r amazing teacher Sir ek request thi kya aap ye topics bhi cover karenge please sir Basic physical design of simple Gates and Layout issues. Layout issues for CMOS inverter, Layout for NAND, NOR and Complex Logic gates, Layout of TG, Layout optimization using Eular path. DRC rules for layout and issues of interconnects

[@ExploreElectronics]

Good explanation.

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[@arunpandi22356]

Good lecture sir thank you so much

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Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

[@gairick9]

11:30 how does static cmos regain Vdd when i/p n-mos is turned on?

[@arunpandyan8173]

Good lecture video sir

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Your positive comments motivates me, my goal is to create largest community of engineers in entire globe, so please help me for that by sharing this lecture series(playlist) with your friends in social media (watsapp, telegram etc). Thanks and welcome 🙏

[@sandeepkarne8407]

sir can u make a video on this topic "Basic Principles of Pass Transistor Circuits Logic “1” Transfer with derivation of it" me really struggling a lot to undestand it

[@IshitaGupta-xx9pv]

Thank you sir for this

[@EngineeringFunda]

Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

[@IshitaGupta-xx9pv]

@@EngineeringFunda Sure sir, I will definitely recommend this playlist to my friends

[@aniketrajapure8251]

Sir at 5:35 u said nmos will get on how ?? Please tell

[@demonslayer3683]

Logic is given to nMos from the previous output. That's why

[@sumitpahuja2858]

why 2*Vtn instead of Vtn in case of Clock =1 and Vin =1...?????

[@sohamroy7668]

Same question

[@VeeralaKrishna-od1pq]

Sir could you please tell how much value we can put for the capacitor

[@aniketrajapure8251]

3:42 by mistake you said pmos that's nmos .

[@ravindraparmar6653]

Wrong concept...domino logic comes because in dynamic logic clock has some delay due to which error occurs...

[@44srijanpramanik22]

Why 2vtn