Clock Skew Solved Problem (Digital Electronics) | Quiz # 500

[@allaboutelectronics-quiz]

For more information about the clock skew, watch this video: kzbin.info/www/bejne/fpvJe4Gahc19d6csi=LySqlxsK8HnUPHki For more information about the setup time and hold time, check this video: kzbin.info/www/bejne/aaWbn5eOZ82kfqMsi=5u3-twKU2HIBib66 For more videos on Digital Electronics, check this playlist: kzbin.info/aero/PLwjK_iyK4LLBC_so3odA64E2MLgIRKafl&si=Mgl5JcQqywvPdKlv

[@mayurshah9131]

Excellent 🎉🎉

[@aamir99204]

Sir what if there was another flip flop followed by these two flip flops? how will we then calculate that?

[@allaboutelectronics-quiz]

It depends how the circuit is connected. Whether the output of the first and second flip-flop are going into next combinational block. Or the output of only second flip-flop is going to the combinational logic block. In later case, you need to find Δ₂ - Δ₃ . In the earlier case, (where both outputs are going into next combinational block where third flip-flop is connected), you need to consider the TL and Ts of both combination block.

[@SatvikkumarRameshbhaiPatel]

4:39 Tcomb = 2ns. There's a mistake right?

[@allaboutelectronics-quiz]

TL and Ts both are Tcomb. One is maximum path length delay and another one is minimum path length delay in the combinational circuit. Here to find the minimum required clock skew corresponding to worst case scenario, minimum combinational delay (Ts) was considered.