Same answer can be get by just simply apply kvl to output loop !
@chinni9494 күн бұрын
As given Vce = 0.2 v and by assuming it is operating in saturation region.. we can get that
@surendrakverma5555 күн бұрын
Thanks Sir 👍
@surendrakverma5555 күн бұрын
Good 👍
@surendrakverma5555 күн бұрын
Thanks Sir 👍
@surendrakverma5555 күн бұрын
Thanks Sir 👍
@surendrakverma5555 күн бұрын
Thanks Sir 👍
@surendrakverma5555 күн бұрын
Thanks Sir
@surendrakverma5555 күн бұрын
Very good 👍
@surendrakverma5555 күн бұрын
Good 👍
@fantomwolf18416 күн бұрын
How are (8,12) and (10,14) prime implicants when there is a bigger group of 1's in (12,13,15,14) wouldn't that make them implicants?
@allaboutelectronics-quiz5 күн бұрын
I think you mean to say a group of (8,12,10,14). Yes, that's true. Since (8,12) and (10,14) are covered by the group of (8,12,10,14) so they are implicant.
@SatvikkumarRameshbhaiPatel8 күн бұрын
4:39 Tcomb = 2ns. There's a mistake right?
@allaboutelectronics-quiz7 күн бұрын
TL and Ts both are Tcomb. One is maximum path length delay and another one is minimum path length delay in the combinational circuit. Here to find the minimum required clock skew corresponding to worst case scenario, minimum combinational delay (Ts) was considered.
@Att_kamalhasan14 күн бұрын
Sir this question from which exam or which book?
@MSDHZAHEEMI20 күн бұрын
Sir,0.5A?
@Tharun-Kumar21 күн бұрын
TG GENCO 2024
@Communityy21 күн бұрын
Got it right.. keep it up dude 😎
@Communityy23 күн бұрын
Can it be like.. Total current I = 1/5 Let current flowing through 500 is I1 and 800 = I2 Then applying KVL And solve the two eq. formed Please clarify ... I'm terribly confused.. just wasted my 1 hr on this question :(
@mayurshah913126 күн бұрын
Excellent as usual sir ji
@user-tm7xd4im5m26 күн бұрын
Nice explain... Clear idea... ❤❤❤
@allaboutelectronics-quiz26 күн бұрын
For more information, related to feedback amplifier, check these videos: 1) Introduction to Feedback Amplifier: kzbin.info/www/bejne/lZCbl2l3jcqhj9Esi=noxzqqORTa7ZWOxL 2) Effect of Negative Feedback on Amplifier Characteristics: kzbin.info/www/bejne/fn3RgHiJfpaYptUsi=_2wZyYjbpE8HfWVE
@are.jpg.png.27 күн бұрын
Sir please make a video on sample and hold circuits (for GATE exam)
@allaboutelectronics-quiz27 күн бұрын
Yes, thats the only remaining topic in digital electronics. And will try to cover it soon.
@Att_kamalhasan28 күн бұрын
Is this previous gate question?
@allaboutelectronics-quiz28 күн бұрын
As far as I know, it is not a GATE question.
@are.jpg.png.29 күн бұрын
Sir at 2:56 can you please explain why output of SR latch are not complement of each other here? I understood the answer but I had this doubt. Kindly clarify.
@allaboutelectronics-quiz29 күн бұрын
In NOR based SR latch, as specifically for NOR gate, when any one of the input is 1, then its output is 0. So, here since one of the input of both the NOR gate is 1. Therefore, both Q1 and Q2 will be 0. I hope, it will clear your doubt.
@are.jpg.png.29 күн бұрын
@@allaboutelectronics-quiz Thank you, sir.
@siriyanamadala1923Ай бұрын
Thank u so much sir...
@rahulpradhan09Ай бұрын
For Vo1, isn't the waveform from -π/5 to 0 should also be positive??
@allaboutelectronics-quiz29 күн бұрын
Here when you turn ON the circuit, then initially it has been assumed that, all the outputs are zero. Therefore, before t = 0, the Vo1 is also zero
@sanjayshah9838Ай бұрын
V.Good as usual 🎉🎉
@allaboutelectronics-quizАй бұрын
_For more solved problems on op-amp, check this playlist:_ kzbin.info/aero/PLH9R5x7JVXCFFScqREEGiFCSyKVM3RTM8&si=iBd4zhZr27LfoFTK _For more information about the feedback amplifier, check this video:_ kzbin.info/www/bejne/lZCbl2l3jcqhj9Esi=wJkJyKRqqDz3pATN
@sanjayshah9838Ай бұрын
Very Very Nice 👍
@allaboutelectronics-quizАй бұрын
For more solved problems on Network Theorem, check this playlist: kzbin.info/aero/PLH9R5x7JVXCEvlSCakgkrfdHfxBU25MYf&si=9m4lbPjXxAqK0VKw For more videos on Network Analysis, check this playlist: kzbin.info/aero/PLH9R5x7JVXCG8nhH8LxTQcwGu-9vMLsE4&si=ZmM9qVbWzDLie3YD
@mmh1922Ай бұрын
You assumed active region but you did not validate the assumption.