CMOS Capacitors, Miller Effect, GBW, fT, Analog CMOS Layout

In this video, I review CMOS capacitive effects followed by a review of the Miller Effect. This is used to show that Cgd can have significant impact on the bandwidth even though it is smaller than Cgs. Layout to reduce Cdb is shown. Ft and GBW are reviewed and compared.

[@sHrG78]

One of the best profs in Concordia University!

[@SatishJaiswalictish]

So simply explained. Thank you!!!

[@user-jt4xc4op6b]

Мдааа готовлюсь к экзамену, спасибо за видео))

[@abuhenamd.nazirhossain4514]

It's very helpful. Do you have materials that describe the overlap capacitance when the transistor is in off state?

[@kavehdehno2331]

Great video! Is it possible to make one for noise analysis?

[@gyrtaz]

can i avoid gate capacitance effects lowering pull-down resistance?

[@abhijithprabha6377]

useful

[@zynthos9]

So the miller gap, in a case where an inverter input is going 0->1, might cause the output to jump up a little big (input coupled to output)?

[@007viviadam]

Zambia95 Can you please elaborate as to how that phenomenon works. I can't, for the life of me, figure out how the voltage spike drops back to the supply voltage after a moment. Also how does the spike at Vss go below 0 when Vss is 0.