CMOS Inverter Layout Using FINGERS.

[@bhattu.karamchand3411]

Thanks

[@dr.hariprasadnaikbhattu]

Welcome

[@akashkale8278]

Sir can you make a video on 2:1 mux layout

[@dr.hariprasadnaikbhattu]

Hi, I will try

[@umeshsinha6388]

hey sir umesh here sir i have completed my project 3 bit ripple carrry adder i have checked Drc and found no error on that but i am finding error in lvs check it is because of when i imported layout of nand and xor gate and try to connect them then for 3 bit full adder cin and my other pin in layout block which is imported i am getting net1 net2 net3 like wise wire with same metal .in lvs check that is only problem . i have found no extraction error in lvs .it will be great if you help us in this problem please sir.

[@dr.hariprasadnaikbhattu]

I could not get what you are asking

[@dr.hariprasadnaikbhattu]

Net1, net2 could the wire you used to connect nand and exor layout

[@abhaysinha7386]

@@dr.hariprasadnaikbhattu hello sir sorry my english is not that much strong . when we imported nand gate and xor gate for making 3 bit rca then the pins of nand gate and xor gate like A,B are present inside the block which has been imported . when i am trying to connect like A to A1 then the wire which i have drawn from A to A1 is written net1 or any net . which is got detected by lvs as error .

[@abhaysinha7386]

the same lvs error i have got while making xor gate using nand gates layout block wire name is written like net1 net2 .

[@rahulbhattu7661]

Thanks

[@dr.hariprasadnaikbhattu]

Welcome