How to correctly build a 4-input NAND gate?🤔

Very helpful. Waiting for more videos on CNFET

Hello sir can we do process corner simulation of low noise amplifier

the above simulation is WSNM or RSNM can you show me how to draw those 2 simulations of SRAM 6T

very informative and very helpful! thank you so much!!

sir which parameter if we vary to reduce power consumption in the CNTFET list

how do we do DC analysis for CNTFET of Ternary NAND Gate

Sir in delay calculation you have consider only one rising nd falling edge but we need to consider viceversa also na, and we need to do average of it. Am i correct? please clarify if i am wrong.

Hi @Hari, Can you do one more section for who are newly entry for ckt design Can you make a digital design and analog design Tq for your efforts tq tq

Sir i can't find assura in the option. I have a option called calibre . Is it the assura ?

can we do PVT analysis by using this verillog-A file, if so how can we do please make a video

how Do we calculate power,delay,PDP,EDP in the ternary logic

sir by using vpwl how we can set period and pulse width , in case of AND gate how we can check all possibilities

Thank you sir for your valuable insights, it is very useful for me to start my work in this area.For doubts clarification can i have your mail id or any contact information for futyher doubt clarifications. Tanking you

Thank you a lot! Can you please provide the Hspice software?

Sir please make a video on how to calculate read and write power in 12t SRAM

Sir please make a video on how to calculate read power and wirte power in 6t SRAM

how you get cntfet in cadence

Sir please do a video on how to calculate Read power and Write power of an 6T SRAM cell

Sir please do a video on how to calculate SNM of 6T SRAM cell

Sir can you u please send me the specifications of this? I needed it for my mini project

thanks sir

Hello Sir. Could you guide me how to calculate the switching power of d flip flop in Cadence Virtuoso ? Thank u very much Sir.

Sir how to calculate powers using pwr signal ?

How do you know how these IP blocks work so that you can know how to connect them? Do the vendors such as AMD or Altera provide documentation or you take a course in university about computer architecture to learn about them?

Thank you sir ❤

Respected sir please upload a video on AMS installation and AMS tutorial in cadence virtuoso. Its a kind request sir.

6:33 no amplification in waveforms

Sir i am having problem with the simulation At 22:20 you stopped recording and corrected the error . Can you please tell me what you corrected.

Thank you sir I had problem with runninf ng spice cir files , you helped a lot greatful...

The head line you written RC Circuit Transient Response is mandatory to write it Sir

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The run simulation is giving not responding and asking to close the progress..... How to slove this...?

Thank you!

thanks

Good explanation sir. I have downloaded theTSMC18RF. Im facing difficulty in adding to the library. How to add these sir

in 3:57 how did you pair both pmos ? it doesnt mean that drain of pmos1 and source of pmos2 is connected ?

sir I am getting an error while running adel simulation for the config file, the message is this "error (SFE-23): "input.scs" 17: The instance 'c1' is referencing an undefined model or subcircuit, 'cmodel'. Wither include the file containing the definition of 'cmodel' or define 'cmodel' before running the simulation." I don't know from where to find the file with definition of cmodel what should I do??

Dear sir, I am researcher. I want to talk to you cadence virtuoso.can you please share your details if you don't mine through mail

Sir can you design cmos class AB amplifier output stage design in cadance

Hello sir, could you guide me how to measure set up time and hold time of flip flop in Cadence Virtuoso ? Thank you very much.

sir when i am saving the text file in the folder using both .cir or .sp . I cannot open that file like your r doing it shows error as no module, but i have saved both ngspice and that cir file in the same folder

sir can you create the layout for this

hello sir, i did as you have shown in the video. But, before the launch step we have to save and continue right, there it is showing 2 error in the Vout and the output pin of the NAND gate, how to solve this?

Sir how to get the Diagnostic window

Thank uu sir❤

Sir can you make videos on Sigma delta adc please.

Very good explanation sir, really u nailed it 👏👏

How to input to ap_start in custom IP

How to calculate the leakage current in any MOS circuit using LTSPICE ?