14 күн бұрын
14 күн бұрын
3 ай бұрын
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4 ай бұрын
Пікірлер
@Zaki99-b3q Күн бұрын
can you design a whip antenna for low frequencies ??
@dorinmurmu6482 4 күн бұрын
Sir I am getting distorted output how to solve it
@dr.hariprasadnaikbhattu 2 күн бұрын
Hi, check you have provided input and vdd properly.
@chunghue2565 7 күн бұрын
Sir, looking forward to you video on CML multiplexer
@dr.hariprasadnaikbhattu 4 күн бұрын
I will need some time
@dr.hariprasadnaikbhattu 4 күн бұрын
I will need some time
@nikithaathinamoni7026 8 күн бұрын
Can we calculate upper thershold voltage and lower threshold voltage ? Sir can you make video on this please
@dr.hariprasadnaikbhattu 4 күн бұрын
Hi, are you asking about Hysterisis loop
@nikithaathinamoni7026 4 күн бұрын
@dr.hariprasadnaikbhattu yes sir
@kaverihatti686 8 күн бұрын
Sir I connected board even after implementation, I did not get the VIO and ILA are appeared after bumping the design in the board.
@dr.hariprasadnaikbhattu 4 күн бұрын
Hi, have you assigned the pin of the FPGA boards
@salmanakhter2225 9 күн бұрын
Sir I followed all the steps correctly but my graph not make butterfly.Please help sir
@dr.hariprasadnaikbhattu 9 күн бұрын
Hi, just go through the process once again. I don't know where you are struck
@todayiwill1361 10 күн бұрын
Thank you!
@dr.hariprasadnaikbhattu 10 күн бұрын
Thanks and Welcome for the response
@kaverihatti686 10 күн бұрын
I am working with ZCU7104 board i followed the same procedure, bitstream is generated but after implementation ILA and VIO did not appear.
@dr.hariprasadnaikbhattu 9 күн бұрын
Hi, once bitstream is generated. Have you connected the board for programming or not
@kaverihatti686 10 күн бұрын
Sir can we follow the same procedure to implement the same design in different FPGA
@dr.hariprasadnaikbhattu 9 күн бұрын
Hi, process for any board is same.
@yadnyeshpatil7790 12 күн бұрын
Sir can you please provide me a research paper of this video cause I need for my college project and it's very urgent
@dr.hariprasadnaikbhattu 11 күн бұрын
Hi, I don't have any research paper. It was done as apart of online course. But you can search on internet regarding the Microstrip Patch design.
@avechess 13 күн бұрын
Like!
@dr.hariprasadnaikbhattu 13 күн бұрын
Thanks and Welcome
@francorenatocampanavalderr2109 14 күн бұрын
Very nice explanation! Thanks a lot!
@dr.hariprasadnaikbhattu 14 күн бұрын
Thanks and Welcome
@jamiepham2441 16 күн бұрын
Hi sir, is it possible you can show us how to design cmos AND-OR-inverter + OR-AND-inverter as well. and 2:1 mux with cmos as well. thank you
@dr.hariprasadnaikbhattu 11 күн бұрын
Hi, do you mean in LtSpice or any other tool
@sannaren-ze5jt 17 күн бұрын
Very useful thankyou ❤
@dr.hariprasadnaikbhattu 16 күн бұрын
Thanks and Welcome
@nikithaAthinamoni 17 күн бұрын
sir ,how can we install finfet libraries ?please explain
@dr.hariprasadnaikbhattu 17 күн бұрын
Hi, FinFet Libraries should be available with Cadence tools. Finfet transistor models must be supported by the tool.
@nikithaathinamoni7026 10 күн бұрын
Is 14nm technology is available of finfet? Sir
@nikithaAthinamoni 17 күн бұрын
sir can you explain finfet technology
@dr.hariprasadnaikbhattu 17 күн бұрын
Hi, I think I have answered your question.
@mohamadhawamdeh7901 18 күн бұрын
how we will get 180nm library file
@dr.hariprasadnaikbhattu 18 күн бұрын
Hi, Try this link, It has 130nm, 180nm drive.google.com/file/d/1WdWIs12BQCoKYMo0WV7o3dUoFsi-XGsh/view
@ravi-lm9lo 19 күн бұрын
good explaination sir
@dr.hariprasadnaikbhattu 19 күн бұрын
Thanks and Welcome
@ibrahimmkhawajaa 19 күн бұрын
jeeooo ustaad taaanuuu looooveee
@dr.hariprasadnaikbhattu 19 күн бұрын
Thanks and Welcome
@pushparaj3240 20 күн бұрын
Good explanation sir thank you very much.
@dr.hariprasadnaikbhattu 19 күн бұрын
Thanks and Welcome for the response.
@JSP_1518 22 күн бұрын
The parametric simulation under tool tab is not there, what to do sir ?
@dr.hariprasadnaikbhattu 21 күн бұрын
Hi, It should be under Tool Tab only. I searched all through the tool. I could not find else where. Are you using ADE-L or ADE-XL
@helloworld-m7s 23 күн бұрын
one of the excellent video which is very useful.Thnk u sir❤❤❤❤❤❤
@dr.hariprasadnaikbhattu 22 күн бұрын
Thanks a lot for your response
@krishnanarasimhareddyyeras3024 23 күн бұрын
Thanks for your tutorial, it was helping me to design VLSI major project using AMD vivado 2024.1 version
@dr.hariprasadnaikbhattu 21 күн бұрын
Glad it helped!
@mehvinpk5707 24 күн бұрын
Sir , can you please upload a video to design antenna in hfss with the help of pyaedt
@dr.hariprasadnaikbhattu 21 күн бұрын
Hi, Use this video link as reference kzbin.info/www/bejne/e6elZ6uNrNylqpo
@tsheringwangchuk3371 26 күн бұрын
sir tell me how you get this pcnfet symbol from the cadence
@tsheringwangchuk3371 26 күн бұрын
i didnt get how you get this symbol, i cant find this type of transistor
@dr.hariprasadnaikbhattu 21 күн бұрын
Hi, Use this video link as reference kzbin.info/www/bejne/e6elZ6uNrNylqpo
@dishan3890 Ай бұрын
Sir can you tell me formula for cutting the inset feed
@dr.hariprasadnaikbhattu 21 күн бұрын
Hi, I dont have it now. It was a practical session conducted
@veerabhadrayyakalacharanti4051 Ай бұрын
Good evening sir Here we have to use 45nm technology only or it will work with 180nm technology too And are there any other parameters which should be taken into account. Because I am not getting the output graph for this.
@dr.hariprasadnaikbhattu 21 күн бұрын
Hi, It works for 45nm as well as 180nm. It is not analog block
@samarthpatel2384 Ай бұрын
Hi Sir, This is really helpful! If you can provide a way to download the cadence virtuoso crack, it will be really helpful!!
@dr.hariprasadnaikbhattu Ай бұрын
Hi, try the website www.getintopc.com
@beatriceanha Ай бұрын
sir can u help me?
@dr.hariprasadnaikbhattu Ай бұрын
Hi, I am not in antenna design now
@nathanross5597 Ай бұрын
Thank you for showing the trick for having wire connections that are not visually touching. Implementing an XOR without that is quite cumbersome.
@dr.hariprasadnaikbhattu Ай бұрын
Thanks for the appreciation. Welcome.
@babyushasunkara6293 Ай бұрын
Sir, in pulse can i give pulse width and period in ns and delay,falling, and rise time in ps. Then calculate delay. Sir, i am getting spikes in the output will i run at every failing and rising edge of input. How to remove those spikes
@dr.hariprasadnaikbhattu Ай бұрын
Hi, First question answer is OK and calculate delay. Second check the supply voltage.
@TungGisAup Ай бұрын
sir can we do layout and RC extraction on the above circuit ?
@dr.hariprasadnaikbhattu Ай бұрын
Hi, cntfets gpdk library is not available. What I have used is a Verilog-A model
@suchithareddy953 Ай бұрын
Can you make a vedio on how to download and install cosmoscope into hspice sir
@dr.hariprasadnaikbhattu Ай бұрын
Hi, Hspice and Cosmoscope is a commercial software. Check if you have any crack version on youtube.
@shubhayansarkhel4363 Ай бұрын
Sir if i want to use one tfet device in cadence virtuoso that i have design in tcad how to do that?
@dr.hariprasadnaikbhattu Ай бұрын
Hi, tfet device is a Verilog-A model. Then it can be done cadence
@daksharora2468 Ай бұрын
getting a sqaure cross box during symbol creation, any idea why?
@dr.hariprasadnaikbhattu Ай бұрын
Hi, It is due to any changes made in schematic design. Symbolic design must be check and save
@egorbunakov Ай бұрын
Hi, your videos are very useful. Can you recommend any literature on the use of ip blocks in vivado and just about the possibilities of vivado?
@dr.hariprasadnaikbhattu Ай бұрын
Hi, IP blocks are shown as block designs in many research articles.
@trieu1962 Ай бұрын
how to fix 4] MSLOT1. W.1 MSLOT1.L.1: Metall Slot width/length must be >=0.2 um
@dr.hariprasadnaikbhattu Ай бұрын
Hi, I could not get what you are asking for
@trieu1962 Ай бұрын
@@dr.hariprasadnaikbhattu it is an error when i check DRC
@suchithareddy953 Ай бұрын
Good morning sir. Can you do an vedii on how to download and install HSPICE in to PC
@dr.hariprasadnaikbhattu Ай бұрын
Hi, HSPICE is not free it is commercial.
@akshaybhargav1086 Ай бұрын
Sir, can we run DRC, and LVS using Calibre in the Cracked version of Cadence? If so can you please make a video or can you please mention the steps to run the Calibre Please Sir
@dr.hariprasadnaikbhattu Ай бұрын
Hi, you can run DRC, and LVS using Calibre. But you require calibre rule file. I could not find it in cracked version.
@akshaybhargav1086 Ай бұрын
@@dr.hariprasadnaikbhattu Okay Thank you Sir
@akshaybhargav1086 Ай бұрын
Sir, if I didn't detach the body from the transistors, should I use a separate Via to connect the sources of the transistors to VDD, and GND? Also I saw a method where we draw a Nwell patch over the pmos. Why do we have to do that?
@dr.hariprasadnaikbhattu Ай бұрын
Hi, Since MOS has four terminals. Schematic has 4 terminals. Layout should have 4 terminals. Else leads to LVS error. Alternate method used NWell patch because it is designed using individual layers.
@akshaybhargav1086 Ай бұрын
@@dr.hariprasadnaikbhattu So does that depend on the PDK we use? Also if I didn't detach the body from the transistors, should I use a separate Via to connect the sources of the transistors to VDD, and GND?
@venkat0536 Ай бұрын
How to load file in assura technology..? Sir
@dr.hariprasadnaikbhattu Ай бұрын
Hi assura technology file comes with gpdk. Use library path editor
@Ritik_Yadav07-p6f Ай бұрын
Please do a video on DRAM 3T
@dr.hariprasadnaikbhattu Ай бұрын
Yes I will need time
@Ritik_Yadav07-p6f Ай бұрын
@@dr.hariprasadnaikbhattu ok sir 👍
@venkat0536 Ай бұрын
How to post in linkedin sir after completing this nand tutorial, and what are the major points we are highlighted and it's(analog and digital both we are mentioned..?) on the linkedin platform I'm confused ..?? Could you tell me sir..? Some major highlighting points...!!
@dr.hariprasadnaikbhattu Ай бұрын
Hi, are asking about the video. If you have created use the web post. your youtube link to post on linked in
@venkat0536 Ай бұрын
@@dr.hariprasadnaikbhattu no sir I'm just posting photos for the results..!! All in linkedin like PDF..,,
@abhishekpatel3246 Ай бұрын
sir i am getting distorted output
@dr.hariprasadnaikbhattu Ай бұрын
Hi check you have provided the vdd and ground. Also see the direction drain and source
@vertebrae_info Ай бұрын
Ok bro
@dr.hariprasadnaikbhattu Ай бұрын
Thanks and Welcome
@debasishmohanta8952 Ай бұрын
I have downloaded but while running it shows no compatibility mode selected! I am not getting any output. Kindly reply.
@dr.hariprasadnaikbhattu Ай бұрын
Hi, recheck the simulation. Is the windows version 32bit or 64bit
@ismartsankar3096 Ай бұрын
There is no assura option in my cdence. How to proceed further sir?
@dr.hariprasadnaikbhattu Ай бұрын
Hi, NO assura option means there is Calibre options to perform the DRC
@muntasirfahad7797 Ай бұрын
Sir can not find the net name display in options. any other way of turning on net name display?
@dr.hariprasadnaikbhattu Ай бұрын
Hi, while creating layout Connectivity--> Generate All From Source----> Go to I/O Pins Below select Create Label As ---> Text Display.
@ANIKETSINGH-nk7js Ай бұрын
sir how can we add all the three gate to get a full adder sir please add one video on it to draw all the gate and to built a full adder
@dr.hariprasadnaikbhattu Ай бұрын
Hi are you asking for a Layout or Just all gates together with transistors
@GundalaVasanthi-v3m Ай бұрын
Sir pls do vedio on differentail op amp
@dr.hariprasadnaikbhattu Ай бұрын
Hi, need some time working on it