Course : Systemverilog Verification 2 : L5.1 : Basics of Systemverilog Interfaces

[@neelshah5465]

Nice representations

[@SystemverilogAcademy]

Thanks 🙂

[@abhijeetchauhan4111]

@3.46 in module design while clock is taken as intf.clk? I mean the clk is not the property of interface. Dont only clk will do

[@SystemverilogAcademy]

'clk' is an input to the interface and you can use it like 'intf.clk' Clock & reset signal will be inputs to the interfaces in general, ( eventhough its not a must)

[@MrVerilog]

You should be using blocking assignment syntax inside initial procedural blocks and non-blocking in always_ff procedural blocks

[@SystemverilogAcademy]

in always_ff, only non blocking assignment need to be used. In initial block, it depends on the use case.

[@SystemverilogAcademy]

If 'initial' is ever used in a design code, its bad coding stile. initial blocks should ever be used in an RTL code, and I am referring 'initial' wrt TB only.

[@MrVerilog]

@@SystemverilogAcademyIn general, yes, one would not want to use initial blocks in an RTL synthesizable design. However, for some FPGAs you have to use them for certain things. They are recognized and supported by the FPGA vendor tools.

[@SystemverilogAcademy]

@@MrVerilog Yes, Agreed

[@abhishektalukdar1890]

content is good but please be abit prominent while speaking.

[@SystemverilogAcademy]

Thanks for the feedback!