CppCon 2015: Michael Wong “C++11/14/17 atomics and memory model..."

[@riveridea]

Before watching this video, you'd better have read the book c++ concurrency in action or the memory model in Cplusplus reference.

[@gavinchou3022]

This talk introduces the memory model of C++11/14/17 on a high level. The speaker introduces a lot of concepts and definitions of the design of the memory model of C++11/14/17, like: data race introduces sequential consistency, what is memory model. it's worth watching though the content arrangement seems a little messy.

[@che5ari]

I thought that Michael did a pretty good job with this presentation. If people feel that he's going too fast with the slides, we have the option to pause the video and go over them carefully which is well worth doing.

[@Silmarieni]

Really really hard to follow with the jumping between slides and spending less than 2 seconds on some slides. It would have been better to drastically narrow the presentation's reach and take time to explain what was exposed.

[@hungbiu8609]

actually really good talk

[@kwkfortythree39]

What about the specific link for the slides instead of the generic url? Thanks.

[@qwertyuiop-cu2ve]

I don't think the wording "happens-before" makes much sense, given the example in 50:11, if #4 actually physically happens after #1, then there's no way they're going to synchronize with eachother. The load acquire can only get the data of the store release if the store happened early enough compared to the load. The precise timing will depend on scheduling and how much work the threads have to do to get to that point.

[@pavelperina7629]

Hmm. I just don't understand why is sequential ordering slower, when the only difference is that compiler is not allowed to reorder writes (well ... or independent reads). I guess it depends in cases where an atomic variable is used as a spin-lock and all threads need to lock two of them always in order. I'd like to have some real-world examples cause I never used atomic variable as a synchronization mechanism, only as something that can be read and written by multiple threads (e.g. terminate flag, proceed flag in condition variable, etc.). :-( Which is something I expected from this talk. Cause just ordering of instruction likely doesn't have any significant performance impact.

[@tohopes]

36:37 👍 good use of "tomfoolery"

[@robrick9361]

kzbin.info/www/bejne/d2nIdHqFpsypfpY I'd recommend newbies go watch the linked video first before this one.

[@focker0000]

"how dare you!" hahaha