Thanks for your tutorial, Bill. Like the others, they're helping me learn faster and I appreciate the time you've spent making them.
@TRak598 Жыл бұрын
Excellent tutorial, goes straight to the point. Only thing I would say is missing is talking about "grouping" (of inputs), since collapsed groups are codified into their binary sequences, making it easier to evaluate results. But I'm not even sure if this version already had this, so sorry if I'm mistaken.
@BillKleitz Жыл бұрын
I'm glad you find these tutorials useful. As far as grouping of inputs, you'll see more of that in later chapters like 7, 8, 12, and 13.
@anup619thapa5 жыл бұрын
Professor Kleitz, I am teaching myself to program FPGAs in Verilog. This video is invaluable for me, I have learnt to simulate systems and it helps be get better understanding of blocking and nonblocking assignments. I am a little confused on the difference (or similarities or the relationship) between a VWF simulation and Modelsim? Its totally possible this is a dumb question when I find out the answer.
@MilanKarakas5 жыл бұрын
Well, for some reason not working. it say: "Errors occured during modelism simulation. What to do? Where to find error and how to fix it. THnaks.
@iluan_8 жыл бұрын
Thanks for the video, it is just what I needed.
@superqaxclub6 жыл бұрын
Thank you so much. I have been looking for vector waveform alternative on Quartus 13 and this video helped
@BillKleitz4 жыл бұрын
There's plenty of samples of basic gate simulations in chapter 4 and 5. They should clear it up for you.
@MrRiceroni3 жыл бұрын
If you receive this error: "Error (199013): HDL output file name contains a non-existent directory path" try restore defaults to fix it: Simulation -> Simulation Settings -> Restore Defaults ->Save That worked for me!
@nickstanley5064 Жыл бұрын
Short and informative, thanks for the video. It really helped me.
@mostafasabeti39522 жыл бұрын
thank you professor kleitz
@BillKleitz Жыл бұрын
You are very welcome
@sccho16316 жыл бұрын
Thank you very much .. Professor Kleitz.
@FajarSuryawan10 жыл бұрын
What is the difference between this simulation and ModelSim one? When should we use which?
@kmlk19239 жыл бұрын
Fajar Suryawan hi fajar , did you find the answer ?
@dwaipayanray99198 жыл бұрын
sir, how to set the path in EDA tool options... if I perform Run Functional simulation-- shows modelsim altera path not found.. please help sir
@M2JD969 жыл бұрын
Hey, how did you get the vector waveform on v13? I can't find it on mine and people are saying v13 doesn't have support for it starting from v10. So how do you have it on v13? Thanks
@MK-zf6or3 жыл бұрын
thanks for the vid, helped me out in my lab
@kleitzw3 жыл бұрын
I'm glad it was helpful. Does the fact that the video was produced using version 13 cause any problem?
@MK-zf6or3 жыл бұрын
@@kleitzw I actually use version 13 for my college, so yes!
@harishy957210 жыл бұрын
im getting an error saying "Error: (vsim-3170) Could not find 'work.orgate_vlg_vec_tst'. # # Error loading design Error loading design Error.
@andresmata88597 жыл бұрын
Great tutorial, thanks! I find the simulation workflow in Altera completely unintuitive.
@rajiv39822 жыл бұрын
Hi professor, how do I calculate or know the numbers that i should input for the "overwrite clock" ?. I'm trying to figure that out with my vhdl code that I'm still learning on how to do it
@poplu70765 ай бұрын
hey, did you get to know how to do them?
@aarifboy Жыл бұрын
When I run functional simulation I dont see new window with waveform, instead I see message below: Error (suppressible): (vsim-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases. # Error loading design Any suggestions?
@rhornak23812 жыл бұрын
Thanks ! Quick and useful video :)
@BillKleitz Жыл бұрын
You're welcome!
@nabitawaluka28254 жыл бұрын
hello there. please help me with how to draw the timing diagram when given an input waveform "in general" say a 2-input, 4 input of an AND Gate. i have searched the internet but i cant find help. i will appreciate.
@LucasGomesDantas7 жыл бұрын
Good tutorial, worked for me
@kleitzw7 жыл бұрын
Lucas Gomes Dantas I'm glad to see that this tutorial worked for you I was afraid that the newer version of quartus might have had a few differences.
@LucasGomesDantas7 жыл бұрын
Hey, Bill! I'm using Quartus for academic purposes, and the teacher recommended for us to use the version 13.1 of the software. So, I'm afraid we can't tell yet that it works for the newer versions =\ Anyway, it helped me a lot. Thanks!
@kleitzw7 жыл бұрын
Yeah the text book follows version 13 pretty closely. I hope you get to try the other tutorials too
@dandiuszielth4 жыл бұрын
I get an error in simulation when I save as any name other than Waveform.vwf, as if it doesn't find the file name when attempting to start the simulation. Is there any reason for that?
@tonykooliyath33254 жыл бұрын
This might be a little late, but to fix your problem try going to the waveform editor simulation > simulation options and check the Testbench Generation Command and Netlist Generation Command lines. Go to the very end of both, and change the name "waveform.vwf.vht" to "yourfilename.vwf.vht"
@JOonRails4 жыл бұрын
Dude you just saved my night with this comment. I had no idea how to change the file to make it work. Thank you!!
@giancarlokuosmanen97233 жыл бұрын
@@tonykooliyath3325 Thanks a bunch man! You just saved my arse, haha.
@mathiazhaganvenkatachalam54142 жыл бұрын
Hi sir, Thanks for the wonderful tutorial, will i be able apply different values for the specific input on various time, such as for input A in 2ns, 6ns, 10ns please help me out in this specific problem sir
@israelperezvicente17473 жыл бұрын
Thanks you Professor
@gerardobriseno44733 жыл бұрын
Very helpful, thank you.
@BillKleitz Жыл бұрын
You're welcome!
@princessdanicaaldovino15169 жыл бұрын
clear explanation.thank you!
@jvnino60863 жыл бұрын
hello... how can I resolve following problem: Error: C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vlog failed.
@MMoreau6 жыл бұрын
The main problem is the limited end time to 100us for the simulation. For this reason i still use Quartus V9.
@vedantchikhale16867 жыл бұрын
Thank you Professor 👍
@abdeljabbarcherkaoui21025 жыл бұрын
How I can visualize variables and signals on the waveform or any other means; thank you
@xaizard9 жыл бұрын
Muito bom, tudo o que eu queria saber.
@nourhh_3 жыл бұрын
what will be the grid size and the end time if i have 16 var?
@Danilego5 жыл бұрын
There's no "University Program VWF" option on mine! There are only 3 file options in the Verification Category
@BillKleitz5 жыл бұрын
Install Version 13 to see the same features shown in the video.
@Danilego5 жыл бұрын
@@BillKleitz I installed version 13.0 and it worked! Thanks!
@patrickyip20052 жыл бұрын
Thanks
@BillKleitz Жыл бұрын
Welcome
@josemiguelsalgadoescuadra60029 жыл бұрын
I've noticed the simulator always tries the verilog format by default (>> quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog Top)... even if you have VHDL on the EDA Tool Settings in Quartus II. Does anyone know a way to simulate purely VHDL designs? I always end up getting ** Error: (vlog-7) Failed to open design unit file "Top.vo" in read mode, which is due to the fact that my compilation creates Top.vho as it is a VHDL only project.
@PTNLemay5 жыл бұрын
Is it possible to create a more "live" simulation. One where we could switch the values of the inputs and see the output change accordingly. It's a bit of a hassle to have to recreate the entire simulation every time I want to alter one of the values.
@abhinavram79202 жыл бұрын
Ig you have to write a code for the testing process too?
@JumpingMonkeysGR5 жыл бұрын
guys if i have the waveform how can i find the function?
@clarisscrisol71347 жыл бұрын
what if i use relay to simulate>
@phoenixs310 жыл бұрын
theres not even an option to create that new file in mine!! i need it for tomorrow any chance you could help?
@joshandseb10 жыл бұрын
well this is a little late then but, after version 9.1 they got rid of the waveform simulator
@billkleitz196310 жыл бұрын
Josh P Quartus Version 13.0 and newer has the vector waveform simulation capability as shown in this VideoCast.
@robertohurtado64587 жыл бұрын
good tut my friend
@elwind76210 жыл бұрын
I try this and it takes forever stuck on top level module on the loading of the functional simulation... RAGE
@salmankhanbakhtawar64924 жыл бұрын
Thanks a lot sir
@BillKleitz3 жыл бұрын
You're welcome!
@TheTimoNizor9 жыл бұрын
Is there maybe a way to get a truth table for a circuit that has been built on Quartus 13.0?
@BillKleitz9 жыл бұрын
The easiest way to produce a truth table is with NI MultiSim.
@TheTimoNizor9 жыл бұрын
Woah Thanks for the fast reply! And I got NI MultiSim, but I don't know to make a truth table from Quartus to MultiSim. Im kinda new to this program.
@vynguyenhoangquoc27023 жыл бұрын
what does offset mean?? Please explain it to me
@kleitzw3 жыл бұрын
In this case, offset is the time in seconds that the waveform is delayed before starting it's cycle. For example if your period is one microsecond and you offset one of the waveforms by 0.1 microseconds you'll see that the waveform is delayed by a tenth of a period.