Tutorial to write and simulate first program in Quartus II 2015.0v using Verilog language

Please subscribe this channel if you find this video useful.and visit digitalsymol.bl... more information

[@nguyentriet5721]

Thank you very much. With your instruction, I finished my first homework about writting Verilog code in Quartus.

[@KaushikBiswasDipto]

Those keyboard click sounds were so annoying. You should've muted that too as you've done with your voice.

[@XekronZ]

Thanks for the video. It was helpful to me.

[@fpgawork]

+XekronZ wellcome brother

[@spikebush8016]

I meet some problems as the video do. When I run the file "Waveform.vwf", it suggests that "completed successfully" and "**** Running the ModelSim simulation **** G:/alter modelsim/modelsim_ase/win32aloem/vsim -c -do Test.do". However ,after that,there is nothing and the output signal has no changes. What's the problem? Is there anyone could help me?

[@spikebush8016]

Determining the location of the ModelSim executable... Using: G:\alter modelsim\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog Test -c Test --vector_source=G:/Quartus/quartus/project/Waveform.vwf --testbench_file=G:/Quartus/quartus/project/simulation/qsim/Waveform.vwf.vt Info: ******************************************************************* Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, Altera MegaCore Function License Info: Agreement, or other applicable license agreement, including, Info: without limitation, that your use is for the sole purpose of Info: programming logic devices manufactured by Altera and sold by Info: Altera or its authorized distributors. Please refer to the Info: applicable agreement for further details. Info: Processing started: Tue Mar 12 10:41:37 2019 Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog Test -c Test --vector_source=G:/Quartus/quartus/project/Waveform.vwf --testbench_file=G:/Quartus/quartus/project/simulation/qsim/Waveform.vwf.vt Info (201000): Generated Verilog Test Bench File G:/Quartus/quartus/project/simulation/qsim/Waveform.vwf.vt for simulation Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 493 megabytes Info: Processing ended: Tue Mar 12 10:41:38 2019 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory=G:/Quartus/quartus/project/simulation/qsim/ Test -c Test Info: ******************************************************************* Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, Altera MegaCore Function License Info: Agreement, or other applicable license agreement, including, Info: without limitation, that your use is for the sole purpose of Info: programming logic devices manufactured by Altera and sold by Info: Altera or its authorized distributors. Please refer to the Info: applicable agreement for further details. Info: Processing started: Tue Mar 12 10:41:39 2019 Info: Command: quartus_eda --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=G:/Quartus/quartus/project/simulation/qsim/ Test -c Test Info (204019): Generated file Test.vo in folder "G:/Quartus/quartus/project/simulation/qsim//" for EDA simulation tool Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 493 megabytes Info: Processing ended: Tue Mar 12 10:41:40 2019 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** G:/Quartus/quartus/project/simulation/qsim/Test.do generated. Completed successfully. **** Running the ModelSim simulation **** G:/alter modelsim/modelsim_ase/win32aloem/vsim -c -do Test.do

[@mujiuyan4796]

Thanks so much. It was helpful to me.

[@vamsiparsa1547]

I am getting error after clicking the "Run functional simulation" .upto this all gone well ,but I am stucked at this point please help me with this

[@chikwuntony]

useful for us.Thanks Muhammad Aslam

[@balamuruganv818]

am not getting the University Program VWF ..can u help me?

[@ImekxD]

its not about programming, its about describing connections :D

[@ahmadirtisam9593]

yes it's about modelling or prototyping

[@patelkeyurkumar6027]

hello sir, please tell me which link to download this software

[@luisfernandomontoya6284]

Thanks Sir!. Great Video

[@lilcax1324]

Ur a beast

[@mehmetginger]

Krall

[@sudarsanreddy2931]

**** Generating the ModelSim .do script **** E:/pwm/simulation/qsim/pwm.do generated. Completed successfully. ModelSim executable not found in E:/pwm Error. sir, thakyou for your presentation , i am getting error like in functional simulation, how to resolve it sir.

[@elainelif]

Hello,did you find a solution for this error? I'm having the same issue right now.

[@mliu100]

Thanks so much!

[@fpgawork]

Thankyou for the appreciation

[@elabbassihicham5418]

THANKS FOR THE VIDEO

[@muzafferozkan6720]

Thanks

[@ernestoti8708]

THANK YOU SIR

[@משהכהן-ש6ה]

thanks.