Data types in Verilog | #5 | Introduction | Verilog in Hindi

Data types in Verilog | #5 | Introduction | Verilog in Hindi | VLSI Point

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Data type is a classification that specifies which type of value can be assigned to a variable and what kind of mathematical operation can be applied to the data type.
In Verilog there are mainly two data types
1. Register data type
2. Net data type
Register represents data storage elements. It is a variable that can hold a value. Nets represent connections between hardware elements.
It must be continuously driven i.e. cannot be used to store the values.
Don't miss the HDL introduction chapter:
Introduction to HDL | What is HDL? | #1 | Verilog in Hindi
• Introduction to HDL | ...
Level of abstraction in Verilog | #2 | Verilog in Hindi
• Level of abstraction i...
Modules and Instantiation in Verilog | #3 | Verilog in Hindi
• Modules and Instantiat...
Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in Hindi
• Simulation, Synthesis ...
Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar

Пікірлер: 15

@reshmathakur1025 3 жыл бұрын

Valuable content 👍 👍

@vlsipoint 3 жыл бұрын

Thanks for watching!

@satendramane5171 2 жыл бұрын

Really very nicely explained. If you have more lectures on various examples using VERILOG then please share with us.Can you please also explain the designing of digital filters like FIR & IIR using VERILOG?

@utkarshsingh3487 3 жыл бұрын

nicely explained ! would like to see more videos on VLSI and Electronics

@udayawalkar5795 2 жыл бұрын

"bina kisi delay ke start karte hai" 👍

@neo-cw3nl Жыл бұрын

Thankyou Sis for these efforts :)

@Peakspeaks Жыл бұрын

Mam you have done a fabolous job. MAM please make playlist where examples and complex related to verilog solves

@aayushgupta5590 3 жыл бұрын

Can we please have reasons for why input port is of net data type inside a module but it can even be reg when it is present outside the module??? and same for output and in-out ports.