Data types in Verilog | #5 | Introduction | Verilog in Hindi | VLSI Point

[@neo-cw3nl]

Thankyou Sis for these efforts :)

[@reshmathakur1025]

Valuable content 👍 👍

[@vlsipoint]

Thanks for watching!

[@utkarshsingh3487]

nicely explained ! would like to see more videos on VLSI and Electronics

[@satendramane5171]

Really very nicely explained. If you have more lectures on various examples using VERILOG then please share with us.Can you please also explain the designing of digital filters like FIR & IIR using VERILOG?

[@udayawalkar5795]

"bina kisi delay ke start karte hai" 👍

[@Peakspeaks]

Mam you have done a fabolous job. MAM please make playlist where examples and complex related to verilog solves

[@aayushgupta5590]

Can we please have reasons for why input port is of net data type inside a module but it can even be reg when it is present outside the module??? and same for output and in-out ports.

[@rohitjoshi2717]

And your help me fast I need PPT now today

[@raunakkumar6144]

Mam, can you please add pdf download link. It would be easy to revise concepts then.

[@rohitjoshi2717]

Pdf ..And your help me fast I need PPT now today

[@AyubKhan-jk6xt]

Maam can you upload the notes in description

[@nilrathod9840]

can anyone explain, what is the importance of strength level?

[@roopa2618]

Mam if you don't mine can you explain in english only..before videos are in english only🙂

[@udayawalkar5795]

english ki alag playlist hai !