Gate Level Modeling | #11 | Verilog in Hindi | VLSI Point

[@nabarunroy722]

The course is really helpful maam. Basics of MOSFET would be beneficial .

[@vlsipoint]

Okay Nabarun, I'll try to make some videos on MOSFET basics.

[@sagargujar2968]

Really good explanation mam... U are inspiring me

[@arghaauddy]

Nice video .Detailed Explanation given.

[@utsavgupta746]

Awesome.... Thanks for such a great explanation 👏.

[@vlsipoint]

Thanks for watching! Stay connected ✌

[@chtty5498]

Synopsis tools, System Verilog,UVM,Rtl designing and verification, SoC ,FPGA, ASICS...discussions would benefit all of us mam:)

[@chtty5498]

DDR4, digital IC design, pipelining, CMOS VLSI DESIGN, ASIC FLOW

[@vlsipoint]

Okay, I'll try to make videos on that

[@seoshreemitra3821]

Great explanation plz upload more videos

[@vlsipoint]

Sure Seoshree, videos will be uploaded soon✌

[@chiragpabari6740]

Ma'am pls cover Verilog code for different combinational and sequential circuits .It will be really helpful from exam point of view.

[@AliMuhammad-sm9hx]

great!

[@vlsipoint]

Thanks for watching, stay tuned ✌✌

[@vijaypratapsharma7001]

superb session maam

[@vlsipoint]

Thanks for watching Vijay! Stay connected ✌

[@happytime7798]

Thank you ma'am

[@vlsipoint]

Thanks for watching, stay tuned ✌✌

[@siddharthkumar2274]

Mam you can make tha video on UVM code to basic

[@sentient1640]

2:13 I didn't understand the truth table. It doesn't look like a regular truth table.

[@utkarshsingh3487]

mam, i am not able to understand this truth table at 2:08

[@Yashwant_Chavan]

In Truth table upper side columns i1 side are & (and) operation with row i2 side and result will inside the truth table.👍

[@JAKU5963]

ma'am, aap system verilog(SV) per video banao from basics. thank you.

[@arshadshaikh9014]

Plz make the video with practical using the verilog code in the system

[@hashimchaudhary208]

ma`am you can make system verilog tutorial also🙂

[@BHAX]

why is the output for bufif1 x when input =z and ctrl=z

[@ayushbhargava4998]

Mam,What is the order to write the code like in the last example of circuit u took a1 then x1 then o1 and then a2.....is there any reason for it or we can take any order

[@mohdafroz043]

Mam,I can't understand the use of wire w1 so please explain in detail

[@user-uz8wq4xn2l]

mam telegram link is notworking ,how to get the pdf notes?

[@laxminarasimha1821]

mam please try to explain the truth table also

[@vlsipoint]

okay

[@rishabhsahu386]

Mam i really appreciate your efforts, these videos are awesome But it's a request mam, please increase the frequency of uploading videos.

[@vlsipoint]

Yes Rishabh, I always try to maintain the continuty but sometimes bcz of college work it would be difficult. Don't worry, videos will be uploaded and verilog course will be completed soon.

[@rishabhsahu386]

@@vlsipoint Alright mam, i understand . No worries.

[@codewithanonymous1645]

Mam please complete it in 1week

[@codewithanonymous1645]

Mam my exam is there

[@vlsipoint]

am trying my best for the course satyam but i am quite bussy right now. I will upload rest of the videos as soon as possible. so stay tuned and All the best for your Exams.

[@codewithanonymous1645]

Can you provide notes

[@mathema5153]

@@vlsipoint please upload more videos