DC Bias of Ceramic Capacitors in 5(ish) Minutes

This video covers a very under-discussed topic that affects virtually every modern circuit. The DC bias effect of ceramic capacitors can dramatically reduce the capacitance they have.
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[@cosminnci]

I would love to see more of this kind of content. thank you.

[@Abdulaziz-tt7rp]

Good content 👍🏽

[@Max-hc4li]

Great video, I would suggest linking stuff you talk about in the description, like simsurfing in this case

[@Bob-zg2zf]

nice to see you again

[@jackbourne7269]

Excellent points. I typically use 3x derating on the capacitors, but sometimes this isn't feasible at higher DC bias voltages. For a 5V rail, I try to use >16V cap & for 12V, I tend to use 35V. This is my rule of thumb but your point about using SimSurfing to check the actualy working capacitance is the way to go for robust design. Using largest capacitance in smallest package is often the way to go as well but some parts arent available in various charcteristics like soft-termination or AEC-200 certification.

[@TomLeg]

Excellent explanation of something I've been wondering about!

[@OrbitalCookie]

Very nice video format, and very important information presented in succinct way. Me likes! :)

[@BHBalast]

Thanks for sharing your knowledge, now I have to check out this program :D

[@EfraAv]

Please keep it up, I loved this format and of course the content

[@edgeeffect]

And here i am blissfully living in a world of "ideal" components and you come along with your "real world" and take another chunk of my innocence away. ;)

[@osmanpasha_diy]

Thank you for the video! So, for energy storage, they are not very useful, right?

[@gsuberland]

I wrote about the underlying physical mechanism for this recently. Class II capacitors use a barium titanate dielectric which undergoes a process called spontaneous polarisation reversal inhibition. The dielectric's magnetic domains within the lattice are randomly polarised when no electric field is applied - this is called spontaneous polarisation. When you apply an electric field, the domains start to align their polarities with it, altering surface charge, and this is where the high dielectric constant and capacitance arises from. The change from random polarisation to field-aligned polarisation in the presence of an electric field is called spontaneous polarisation reversal. However, as the DC electric field strength increases, it causes an inhibition of the ability of the magnetic domains to go back to their spontaneously polarised state in the presence of a superimposed AC field. DC bias essentially exhausts the number of domains available for spontaneous polarisation reversal, and since the effective capacitance is tied to the ability to align the domain polarities with the applied electric field, this results in significant capacitance derating. This same process results in hysteresis effects and domain wall heating (where adjacent domains have differing polarities), which makes Class II dielectrics unsuitable for applications with low distortion requirements (e.g. RF). Class I capacitors (e.g. calcium zirconate dielectrics like C0G) don't undergo this mechanism because they aren't spontaneously polarised. When there's no applied electric field, the lattice is non-polar. The lattice only begins to polarise when an electric field is applied, and remains free to realign to an AC electric field almost regardless of DC field strength. The lack of hysteresis also means you get very low distortion and lower self-heating effects. The downside is that the dielectric constant in Class I is much lower, so you get far lower total capacitance per unit volume than Class II.

[@agnelomascarenhas8990]

Thank you for elaborating on the mechanism, I just knew Class II capacitor dielectrics to be ferroelectric. High dielectric constant, but poor tolerances and high temperature coefficient.

[@agnelomascarenhas8990]

Thank you for educating us, useful info. For Engineers 1) the temperature coefficient curve is parabolic?. minimum near room temperature and worsening with temperature extremes 2) wide initial tolerance typically +20 to -60% 3) voltage derating of capacitance. As voltage is applied, the capacitance falls and severely to the extent of say 60%. 4) Microphonics sensitivity. After reading some other comments on the material, I would be careful to watch out that the dielectric permittivity becoming real at higher frequencies and behaving resistive. useful dielectric material as long as you are aware of its quirks.

[@retireeelectronics2649]

Very nice video, I was wondering on the trade-offs.

[@DeanTheDoctor]

Incredibly helpful. Thank you for making this video brother. 😄🌎✨

[@YousefAboAnNour]

Thank you very much for this content

[@Nebulorum]

Really like this format. Just make me less comfortable with designing 😂

[@stevemercer6976]

The bias effect is unrelated to rated voltage in the same package size. At 5V working voltage the capacitance decrease will be almost identical in a 6V rated 0603 part and in a 15V rated 0603 part. The only mitigating approach is to either use a larger package or a better dielectric.

[@damny0utoobe]

This crushed my dreams, broke my heart 💔

[@szekerespista3758]

How about the DC bias of the C0G class 1 MLCC capacitors?

[@user-ty2uz4gb7v]

So since class 2 ceramic SMD caps are cheap, and come in a very wide variety of capacitance per package size, why not just compensate for the dc voltage bias when choosing your cap capacity? In other words why is DC voltage bias even an issue?

[@Tortuga2321]

I think DEK printer yamaha machine and HELLER 1809 reflow oven

[@glasslinger]

Use tantalums.

[@Theineluctable_SOME_CANT]

Didn't know...